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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-mpc85xx

Browse Source 
- DM_ETH support for P2041RDB, T1024RDB, P5040DS, P3041DS, P4080DS, bug
  fixes
- Add TBI PHY access through MII
- DDR: Rework errata workaround for A008109, A008378, 009942
This commit is contained in:
Tom Rini 2020-06-08 08:51:59 -04:00
commit 08649c3d50
87 changed files with 3111 additions and 86 deletions
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6
arch/powerpc/cpu/mpc85xx/Kconfig
View File

@ -996,6 +996,7 @@ config ARCH_T1023
select FSL_LAW
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
@ -1016,6 +1017,7 @@ config ARCH_T1024
select FSL_LAW
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
@ -1038,6 +1040,7 @@ config ARCH_T1040
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
@ -1061,6 +1064,7 @@ config ARCH_T1042
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008044
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008109
select SYS_FSL_ERRATUM_A009663
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
@ -1089,6 +1093,7 @@ config ARCH_T2080
select SYS_FSL_ERRATUM_A007212
select SYS_FSL_ERRATUM_A007815
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A008109
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_ESDHC111
select FSL_PCIE_RESET
@ -1167,6 +1172,7 @@ config ARCH_T4240
select SYS_FSL_ERRATUM_A007798
select SYS_FSL_ERRATUM_A007815
select SYS_FSL_ERRATUM_A007907
select SYS_FSL_ERRATUM_A008109
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_SEC

6
arch/powerpc/cpu/mpc85xx/cpu_init.c
View File

@ -963,8 +963,10 @@ int cpu_init_r(void)
#endif
#ifdef CONFIG_FMAN_ENET
#ifndef CONFIG_DM_ETH
fman_enet_init();
#endif
#endif
#if defined(CONFIG_NXP_ESBC) && defined(CONFIG_FSL_CORENET)
if (pamu_init() < 0)
@ -1028,13 +1030,13 @@ void arch_preboot_os(void)
void cpu_secondary_init_r(void)
{
#ifdef CONFIG_QE
#ifdef CONFIG_U_QE
uint qe_base = CONFIG_SYS_IMMR + 0x00140000; /* QE immr base */
#elif defined CONFIG_QE
#else
uint qe_base = CONFIG_SYS_IMMR + 0x00080000; /* QE immr base */
#endif
#ifdef CONFIG_QE
qe_init(qe_base);
qe_reset();
#endif

98
arch/powerpc/dts/p2041rdb.dts
View File

@ -3,7 +3,7 @@
* P2041RDB Device Tree Source
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/include/ "p2041.dtsi"
@ -15,4 +15,100 @@
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_2 = &phy_sgmii_2;
phy_sgmii_3 = &phy_sgmii_3;
phy_sgmii_4 = &phy_sgmii_4;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_2 = &phy_xgmii_2;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
mdio@e1120 {
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
phy_sgmii_2: ethernet-phy@2 {
reg = <0x2>;
};
phy_sgmii_3: ethernet-phy@3 {
reg = <0x3>;
};
phy_sgmii_4: ethernet-phy@4 {
reg = <0x4>;
};
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_3>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_4>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_2>;
phy-connection-type = "xgmii";
};
mdio@f1000 {
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
};
};
/include/ "p2041si-post.dtsi"

42
arch/powerpc/dts/p2041si-post.dtsi Normal file
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@ -0,0 +1,42 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* P2041/P2040 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
&soc {
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
/include/ "qoriq-fman-0-1g-0.dtsi"
/include/ "qoriq-fman-0-1g-1.dtsi"
/include/ "qoriq-fman-0-1g-2.dtsi"
/include/ "qoriq-fman-0-1g-3.dtsi"
/include/ "qoriq-fman-0-1g-4.dtsi"
/include/ "qoriq-fman-0-10g-0.dtsi"
fman@400000 {
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
enet4: ethernet@e8000 {
};
enet5: ethernet@f0000 {
};
};
};

129
arch/powerpc/dts/p3041ds.dts
View File

@ -3,7 +3,7 @@
* P3041DS Device Tree Source
*
* Copyright 2010 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/include/ "p3041.dtsi"
@ -15,4 +15,131 @@
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases{
phy_rgmii_0 = &phy_rgmii_0;
phy_rgmii_1 = &phy_rgmii_1;
phy_sgmii_1c = &phy_sgmii_1c;
phy_sgmii_1d = &phy_sgmii_1d;
phy_sgmii_1e = &phy_sgmii_1e;
phy_sgmii_1f = &phy_sgmii_1f;
phy_xgmii_1 = &phy_xgmii_1;
phy_xgmii_2 = &phy_xgmii_2;
emi1_rgmii = &hydra_mdio_rgmii;
emi1_sgmii = &hydra_mdio_sgmii;
emi2_xgmii = &hydra_mdio_xgmii;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
fman@400000{
ethernet@e0000 {
phy-handle = <&phy_sgmii_1c>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy_sgmii_1d>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy_sgmii_1e>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy_sgmii_1f>;
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_1>;
phy-connection-type = "xgmii";
};
hydra_mdio_xgmii: mdio@f1000 {
status = "disabled";
phy_xgmii_1: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
phy_xgmii_2: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
};
};
lbc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x1000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
2 0 0xf 0xffa00000 0x00040000
3 0 0xf 0xffdf0000 0x00008000>;
board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p3041ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x30>;
ranges = <0 3 0 0x30>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <9 1>;
mux-mask = <0x78>;
hydra_mdio_rgmii: rgmii-mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <8>;
status = "disabled";
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
};
hydra_mdio_sgmii: sgmii-mdio@28 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x28>;
status = "disabled";
phy_sgmii_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
};
};
};
/include/ "p3041si-post.dtsi"

42
arch/powerpc/dts/p3041si-post.dtsi Normal file
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@ -0,0 +1,42 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* P3041 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
&soc {
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
/include/ "qoriq-fman-0-1g-0.dtsi"
/include/ "qoriq-fman-0-1g-1.dtsi"
/include/ "qoriq-fman-0-1g-2.dtsi"
/include/ "qoriq-fman-0-1g-3.dtsi"
/include/ "qoriq-fman-0-1g-4.dtsi"
/include/ "qoriq-fman-0-10g-0.dtsi"
fman@400000 {
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
enet4: ethernet@e8000 {
};
enet5: ethernet@f0000 {
};
};
};

191
arch/powerpc/dts/p4080ds.dts
View File

@ -3,7 +3,7 @@
* P4080DS Device Tree Source
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/include/ "p4080.dtsi"
@ -15,4 +15,193 @@
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
phy_rgmii = &phyrgmii;
phy5_slot3 = &phy5slot3;
phy6_slot3 = &phy6slot3;
phy7_slot3 = &phy7slot3;
phy8_slot3 = &phy8slot3;
emi1_slot3 = &p4080mdio2;
emi1_slot4 = &p4080mdio1;
emi1_slot5 = &p4080mdio3;
emi1_rgmii = &p4080mdio0;
emi2_slot4 = &p4080xmdio1;
emi2_slot5 = &p4080xmdio3;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
fman@400000 {
ethernet@e0000 {
phy-handle = <&phy0>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy1>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy2>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy3>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy10>;
phy-connection-type = "xgmii";
};
};
fman@500000 {
ethernet@e0000 {
phy-handle = <&phy5>;
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-handle = <&phy6>;
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-handle = <&phy7>;
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-handle = <&phy8>;
phy-connection-type = "sgmii";
};
ethernet@f0000 {
phy-handle = <&phy11>;
phy-connection-type = "xgmii";
};
};
};
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-gpio", "mdio-mux";
mdio-parent-bus = <&mdio0>;
gpios = <&gpio0 1 0>, <&gpio0 0 0>;
p4080mdio0: mdio@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
phyrgmii: ethernet-phy@0 {
reg = <0x0>;
};
};
p4080mdio1: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phy5: ethernet-phy@1c {
reg = <0x1c>;
};
phy6: ethernet-phy@1d {
reg = <0x1d>;
};
phy7: ethernet-phy@1e {
reg = <0x1e>;
};
phy8: ethernet-phy@1f {
reg = <0x1f>;
};
};
p4080mdio2: mdio@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
status = "disabled";
phy5slot3: ethernet-phy@1c {
reg = <0x1c>;
};
phy6slot3: ethernet-phy@1d {
reg = <0x1d>;
};
phy7slot3: ethernet-phy@1e {
reg = <0x1e>;
};
phy8slot3: ethernet-phy@1f {
reg = <0x1f>;
};
};
p4080mdio3: mdio@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
phy0: ethernet-phy@1c {
reg = <0x1c>;
};
phy1: ethernet-phy@1d {
reg = <0x1d>;
};
phy2: ethernet-phy@1e {
reg = <0x1e>;
};
phy3: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
mdio-mux-emi2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-gpio", "mdio-mux";
mdio-parent-bus = <&xmdio0>;
gpios = <&gpio0 3 0>, <&gpio0 2 0>;
p4080xmdio1: mdio@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
phy11: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x0>;
};
};
p4080xmdio3: mdio@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
phy10: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x4>;
};
};
};
};
/include/ "p4080si-post.dtsi"

61
arch/powerpc/dts/p4080si-post.dtsi Normal file
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@ -0,0 +1,61 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* P4080/P4040 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
&soc {
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
/include/ "qoriq-fman-0-1g-0.dtsi"
/include/ "qoriq-fman-0-1g-1.dtsi"
/include/ "qoriq-fman-0-1g-2.dtsi"
/include/ "qoriq-fman-0-1g-3.dtsi"
/include/ "qoriq-fman-0-10g-0.dtsi"
fman@400000 {
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
enet4: ethernet@f0000 {
};
};
/include/ "qoriq-fman-1.dtsi"
/include/ "qoriq-fman-1-1g-0.dtsi"
/include/ "qoriq-fman-1-1g-1.dtsi"
/include/ "qoriq-fman-1-1g-2.dtsi"
/include/ "qoriq-fman-1-1g-3.dtsi"
/include/ "qoriq-fman-1-10g-0.dtsi"
fman@500000 {
enet5: ethernet@e0000 {
};
enet6: ethernet@e2000 {
};
enet7: ethernet@e4000 {
};
enet8: ethernet@e6000 {
};
enet9: ethernet@f0000 {
};
};
};

252
arch/powerpc/dts/p5040ds.dts
View File

@ -3,7 +3,7 @@
* P5040DS Device Tree Source
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/include/ "p5040.dtsi"
@ -15,4 +15,254 @@
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases{
phy_sgmii_slot2_1c = &phy_sgmii_slot2_1c;
phy_sgmii_slot2_1d = &phy_sgmii_slot2_1d;
phy_sgmii_slot2_1e = &phy_sgmii_slot2_1e;
phy_sgmii_slot2_1f = &phy_sgmii_slot2_1f;
phy_sgmii_slot3_1c = &phy_sgmii_slot3_1c;
phy_sgmii_slot3_1d = &phy_sgmii_slot3_1d;
phy_sgmii_slot3_1e = &phy_sgmii_slot3_1e;
phy_sgmii_slot3_1f = &phy_sgmii_slot3_1f;
phy_sgmii_slot5_1c = &phy_sgmii_slot5_1c;
phy_sgmii_slot5_1d = &phy_sgmii_slot5_1d;
phy_sgmii_slot5_1e = &phy_sgmii_slot5_1e;
phy_sgmii_slot5_1f = &phy_sgmii_slot5_1f;
phy_sgmii_slot6_1c = &phy_sgmii_slot6_1c;
phy_sgmii_slot6_1d = &phy_sgmii_slot6_1d;
phy_sgmii_slot6_1e = &phy_sgmii_slot6_1e;
phy_sgmii_slot6_1f = &phy_sgmii_slot6_1f;
hydra_rg = &hydra_rg;
hydra_sg_slot2 = &hydra_sg_slot2;
hydra_sg_slot3 = &hydra_sg_slot3;
hydra_sg_slot5 = &hydra_sg_slot5;
hydra_sg_slot6 = &hydra_sg_slot6;
hydra_xg_slot1 = &hydra_xg_slot1;
hydra_xg_slot2 = &hydra_xg_slot2;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
fman@400000 {
ethernet@e0000 {
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_0>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_slot_2>;
phy-connection-type = "xgmii";
};
};
fman@500000 {
ethernet@e0000 {
phy-connection-type = "sgmii";
};
ethernet@e2000 {
phy-connection-type = "sgmii";
};
ethernet@e4000 {
phy-connection-type = "sgmii";
};
ethernet@e6000 {
phy-connection-type = "sgmii";
};
ethernet@e8000 {
phy-handle = <&phy_rgmii_1>;
phy-connection-type = "rgmii";
};
ethernet@f0000 {
phy-handle = <&phy_xgmii_slot_1>;
phy-connection-type = "xgmii";
};
};
};
lbc: localbus@ffe124000 {
reg = <0xf 0xfe124000 0 0x1000>;
ranges = <0 0 0xf 0xe8000000 0x08000000
2 0 0xf 0xffa00000 0x00040000
3 0 0xf 0xffdf0000 0x00008000>;
board-control@3,0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,p5040ds-fpga", "fsl,fpga-ngpixis";
reg = <3 0 0x40>;
ranges = <0 3 0 0x40>;
mdio-mux-emi1 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&mdio0>;
reg = <9 1>;
mux-mask = <0x78>;
hydra_rg:rgmii-mdio@8 {
#address-cells = <1>;
#size-cells = <0>;
reg = <8>;
status = "disabled";
phy_rgmii_0: ethernet-phy@0 {
reg = <0x0>;
};
phy_rgmii_1: ethernet-phy@1 {
reg = <0x1>;
};
};
hydra_sg_slot2: sgmii-mdio@28 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x28>;
status = "disabled";
phy_sgmii_slot2_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot2_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot2_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot2_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot3: sgmii-mdio@68 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x68>;
status = "disabled";
phy_sgmii_slot3_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot3_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot3_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot3_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot5: sgmii-mdio@38 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x38>;
status = "disabled";
phy_sgmii_slot5_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot5_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot5_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot5_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
hydra_sg_slot6: sgmii-mdio@48 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x48>;
status = "disabled";
phy_sgmii_slot6_1c: ethernet-phy@1c {
reg = <0x1c>;
};
phy_sgmii_slot6_1d: ethernet-phy@1d {
reg = <0x1d>;
};
phy_sgmii_slot6_1e: ethernet-phy@1e {
reg = <0x1e>;
};
phy_sgmii_slot6_1f: ethernet-phy@1f {
reg = <0x1f>;
};
};
};
mdio-mux-emi2 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "mdio-mux-mmioreg", "mdio-mux";
mdio-parent-bus = <&xmdio0>;
reg = <9 1>;
mux-mask = <0x06>;
hydra_xg_slot1: hydra-xg-slot1@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
status = "disabled";
phy_xgmii_slot_1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <4>;
};
};
hydra_xg_slot2: hydra-xg-slot2@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
phy_xgmii_slot_2: ethernet-phy@4 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0>;
};
};
};
};
};
};
/include/ "p5040si-post.dtsi"

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* P5040 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
&soc {
/include/ "qoriq-clockgen1.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman-0.dtsi"
/include/ "qoriq-fman-0-1g-0.dtsi"
/include/ "qoriq-fman-0-1g-1.dtsi"
/include/ "qoriq-fman-0-1g-2.dtsi"
/include/ "qoriq-fman-0-1g-3.dtsi"
/include/ "qoriq-fman-0-1g-4.dtsi"
/include/ "qoriq-fman-0-10g-0.dtsi"
fman@400000 {
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
enet4: ethernet@e8000 {
};
enet5: ethernet@f0000 {
};
};
/include/ "qoriq-fman-1.dtsi"
/include/ "qoriq-fman-1-1g-0.dtsi"
/include/ "qoriq-fman-1-1g-1.dtsi"
/include/ "qoriq-fman-1-1g-2.dtsi"
/include/ "qoriq-fman-1-1g-3.dtsi"
/include/ "qoriq-fman-1-1g-4.dtsi"
/include/ "qoriq-fman-1-10g-0.dtsi"
fman@500000 {
enet6: ethernet@e0000 {
};
enet7: ethernet@e2000 {
};
enet8: ethernet@e4000 {
};
enet9: ethernet@e6000 {
};
enet10: ethernet@e8000 {
};
enet11: ethernet@f0000 {
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
*
* Copyright 2014 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
clockgen: global-utilities@e1000 {
compatible = "fsl,qoriq-clockgen-1.0";
reg = <0xe1000 0x1000>;
#clock-cells = <2>;
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ clock control device tree stub [ controller @ offset 0xe1000 ]
*
* Copyright 2014 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
clockgen: global-utilities@e1000 {
compatible = "fsl,qoriq-clockgen-2.0";
reg = <0xe1000 0x1000>;
#clock-cells = <2>;
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x10: port@90000 {
cell-index = <0x10>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x90000 0x1000>;
};
fman0_tx_0x30: port@b0000 {
cell-index = <0x30>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xb0000 0x1000>;
};
ethernet@f0000 {
cell-index = <0x8>;
compatible = "fsl,fman-xgec";
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
};
xmdio0: mdio@f1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-xmdio";
reg = <0xf1000 0x1000>;
interrupts = <101 2 0 0>;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x08: port@88000 {
cell-index = <0x8>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x88000 0x1000>;
};
fman0_tx_0x28: port@a8000 {
cell-index = <0x28>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xa8000 0x1000>;
};
ethernet@e0000 {
cell-index = <0>;
compatible = "fsl,fman-dtsec";
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
tbi-handle = <&tbi0>;
ptp-timer = <&ptp_timer0>;
};
mdio0: mdio@e1120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe1120 0xee0>;
interrupts = <100 2 0 0>;
tbi0: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x09: port@89000 {
cell-index = <0x9>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x89000 0x1000>;
};
fman0_tx_0x29: port@a9000 {
cell-index = <0x29>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xa9000 0x1000>;
};
ethernet@e2000 {
cell-index = <1>;
compatible = "fsl,fman-dtsec";
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
tbi-handle = <&tbi1>;
ptp-timer = <&ptp_timer0>;
};
mdio@e3120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe3120 0xee0>;
tbi1: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 1g port #2 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x0a: port@8a000 {
cell-index = <0xa>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x8a000 0x1000>;
};
fman0_tx_0x2a: port@aa000 {
cell-index = <0x2a>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xaa000 0x1000>;
};
ethernet@e4000 {
cell-index = <2>;
compatible = "fsl,fman-dtsec";
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
tbi-handle = <&tbi2>;
ptp-timer = <&ptp_timer0>;
};
mdio@e5120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe5120 0xee0>;
tbi2: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 1g port #3 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x0b: port@8b000 {
cell-index = <0xb>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x8b000 0x1000>;
};
fman0_tx_0x2b: port@ab000 {
cell-index = <0x2b>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xab000 0x1000>;
};
ethernet@e6000 {
cell-index = <3>;
compatible = "fsl,fman-dtsec";
reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
tbi-handle = <&tbi3>;
ptp-timer = <&ptp_timer0>;
};
mdio@e7120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe7120 0xee0>;
tbi3: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 1g port #4 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x0c: port@8c000 {
cell-index = <0xc>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x8c000 0x1000>;
};
fman0_tx_0x2c: port@ac000 {
cell-index = <0x2c>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xac000 0x1000>;
};
ethernet@e8000 {
cell-index = <4>;
compatible = "fsl,fman-dtsec";
reg = <0xe8000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
tbi-handle = <&tbi4>;
ptp-timer = <&ptp_timer0>;
};
mdio@e9120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe9120 0xee0>;
tbi4: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman0: fman@400000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
compatible = "fsl,fman";
ranges = <0 0x400000 0xfe000>;
reg = <0x400000 0xfe000>;
interrupts = <96 2 0 0>, <16 2 1 1>;
clocks = <&clockgen 3 0>;
clock-names = "fmanclk";
fsl,qman-channel-range = <0x40 0xc>;
ptimer-handle = <&ptp_timer0>;
muram@0 {
compatible = "fsl,fman-muram";
reg = <0x0 0x28000>;
};
fman0_oh_0x1: port@81000 {
cell-index = <0x1>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x81000 0x1000>;
};
fman0_oh_0x2: port@82000 {
cell-index = <0x2>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x82000 0x1000>;
};
fman0_oh_0x3: port@83000 {
cell-index = <0x3>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x83000 0x1000>;
};
fman0_oh_0x4: port@84000 {
cell-index = <0x4>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x84000 0x1000>;
};
fman0_oh_0x5: port@85000 {
cell-index = <0x5>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x85000 0x1000>;
status = "disabled";
};
fman0_oh_0x6: port@86000 {
cell-index = <0x6>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x86000 0x1000>;
status = "disabled";
};
fman0_oh_0x7: port@87000 {
cell-index = <0x7>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x87000 0x1000>;
status = "disabled";
};
};
ptp_timer0: ptp-timer@4fe000 {
compatible = "fsl,fman-ptp-timer";
reg = <0x4fe000 0x1000>;
interrupts = <96 2 0 0>;
clocks = <&clockgen 3 0>;
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 10g port #0 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x10: port@90000 {
cell-index = <0x10>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x90000 0x1000>;
};
fman1_tx_0x30: port@b0000 {
cell-index = <0x30>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xb0000 0x1000>;
};
ethernet@f0000 {
cell-index = <0x8>;
compatible = "fsl,fman-xgec";
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
};
mdio@f1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-xmdio";
reg = <0xf1000 0x1000>;
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 1g port #0 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x08: port@88000 {
cell-index = <0x8>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x88000 0x1000>;
};
fman1_tx_0x28: port@a8000 {
cell-index = <0x28>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xa8000 0x1000>;
};
ethernet@e0000 {
cell-index = <0>;
compatible = "fsl,fman-dtsec";
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>;
tbi-handle = <&tbi5>;
ptp-timer = <&ptp_timer1>;
};
mdio@e1120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe1120 0xee0>;
tbi5: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 1g port #1 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x09: port@89000 {
cell-index = <0x9>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x89000 0x1000>;
};
fman1_tx_0x29: port@a9000 {
cell-index = <0x29>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xa9000 0x1000>;
};
ethernet@e2000 {
cell-index = <1>;
compatible = "fsl,fman-dtsec";
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
tbi-handle = <&tbi6>;
ptp-timer = <&ptp_timer1>;
};
mdio@e3120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe3120 0xee0>;
tbi6: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 1g port #2 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x0a: port@8a000 {
cell-index = <0xa>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x8a000 0x1000>;
};
fman1_tx_0x2a: port@aa000 {
cell-index = <0x2a>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xaa000 0x1000>;
};
ethernet@e4000 {
cell-index = <2>;
compatible = "fsl,fman-dtsec";
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
tbi-handle = <&tbi7>;
ptp-timer = <&ptp_timer1>;
};
mdio@e5120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe5120 0xee0>;
tbi7: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 1g port #3 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x0b: port@8b000 {
cell-index = <0xb>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x8b000 0x1000>;
};
fman1_tx_0x2b: port@ab000 {
cell-index = <0x2b>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xab000 0x1000>;
};
ethernet@e6000 {
cell-index = <3>;
compatible = "fsl,fman-dtsec";
reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
tbi-handle = <&tbi8>;
ptp-timer = <&ptp_timer1>;
};
mdio@e7120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe7120 0xee0>;
tbi8: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan 1g port #4 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x0c: port@8c000 {
cell-index = <0xc>;
compatible = "fsl,fman-v2-port-rx";
reg = <0x8c000 0x1000>;
};
fman1_tx_0x2c: port@ac000 {
cell-index = <0x2c>;
compatible = "fsl,fman-v2-port-tx";
reg = <0xac000 0x1000>;
};
ethernet@e8000 {
cell-index = <4>;
compatible = "fsl,fman-dtsec";
reg = <0xe8000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>;
tbi-handle = <&tbi9>;
ptp-timer = <&ptp_timer1>;
};
mdio@e9120 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-mdio";
reg = <0xe9120 0xee0>;
tbi9: tbi-phy@8 {
reg = <0x8>;
device_type = "tbi-phy";
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2011 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman1: fman@500000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
compatible = "fsl,fman";
ranges = <0 0x500000 0xfe000>;
reg = <0x500000 0xfe000>;
interrupts = <97 2 0 0>, <16 2 1 0>;
clocks = <&clockgen 3 1>;
clock-names = "fmanclk";
fsl,qman-channel-range = <0x60 0xc>;
ptimer-handle = <&ptp_timer1>;
muram@0 {
compatible = "fsl,fman-muram";
reg = <0x0 0x28000>;
};
fman1_oh_0x1: port@81000 {
cell-index = <0x1>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x81000 0x1000>;
};
fman1_oh_0x2: port@82000 {
cell-index = <0x2>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x82000 0x1000>;
};
fman1_oh_0x3: port@83000 {
cell-index = <0x3>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x83000 0x1000>;
};
fman1_oh_0x4: port@84000 {
cell-index = <0x4>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x84000 0x1000>;
};
fman1_oh_0x5: port@85000 {
cell-index = <0x5>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x85000 0x1000>;
status = "disabled";
};
fman1_oh_0x6: port@86000 {
cell-index = <0x6>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x86000 0x1000>;
status = "disabled";
};
fman1_oh_0x7: port@87000 {
cell-index = <0x7>;
compatible = "fsl,fman-v2-port-oh";
reg = <0x87000 0x1000>;
status = "disabled";
};
};
ptp_timer1: ptp-timer@5fe000 {
compatible = "fsl,fman-ptp-timer";
reg = <0x5fe000 0x1000>;
interrupts = <97 2 0 0>;
clocks = <&clockgen 3 1>;
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x08: port@88000 {
cell-index = <0x8>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x88000 0x1000>;
fsl,fman-10g-port;
fsl,fman-best-effort-port;
};
fman0_tx_0x28: port@a8000 {
cell-index = <0x28>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xa8000 0x1000>;
fsl,fman-10g-port;
fsl,fman-best-effort-port;
};
ethernet@e0000 {
cell-index = <0>;
compatible = "fsl,fman-memac";
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy0>;
};
mdio@e1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy0: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 10g port #0 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x10: port@90000 {
cell-index = <0x10>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x90000 0x1000>;
fsl,fman-10g-port;
};
fman0_tx_0x30: port@b0000 {
cell-index = <0x30>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xb0000 0x1000>;
fsl,fman-10g-port;
};
ethernet@f0000 {
cell-index = <0x8>;
compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>;
pcsphy-handle = <&pcsphy6>;
};
mdio@f1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf1000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy6: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x09: port@89000 {
cell-index = <0x9>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x89000 0x1000>;
fsl,fman-10g-port;
fsl,fman-best-effort-port;
};
fman0_tx_0x29: port@a9000 {
cell-index = <0x29>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xa9000 0x1000>;
fsl,fman-10g-port;
fsl,fman-best-effort-port;
};
ethernet@e2000 {
cell-index = <1>;
compatible = "fsl,fman-memac";
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy1>;
};
mdio@e3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy1: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x11: port@91000 {
cell-index = <0x11>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x91000 0x1000>;
fsl,fman-10g-port;
};
fman0_tx_0x31: port@b1000 {
cell-index = <0x31>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xb1000 0x1000>;
fsl,fman-10g-port;
};
ethernet@f2000 {
cell-index = <0x9>;
compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>;
pcsphy-handle = <&pcsphy7>;
};
mdio@f3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf3000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy7: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x08: port@88000 {
cell-index = <0x8>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x88000 0x1000>;
};
fman0_tx_0x28: port@a8000 {
cell-index = <0x28>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xa8000 0x1000>;
};
ethernet@e0000 {
cell-index = <0>;
compatible = "fsl,fman-memac";
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy0>;
};
mdio@e1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy0: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x09: port@89000 {
cell-index = <0x9>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x89000 0x1000>;
};
fman0_tx_0x29: port@a9000 {
cell-index = <0x29>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xa9000 0x1000>;
};
ethernet@e2000 {
cell-index = <1>;
compatible = "fsl,fman-memac";
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy1>;
};
mdio@e3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy1: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #2 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x0a: port@8a000 {
cell-index = <0xa>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x8a000 0x1000>;
};
fman0_tx_0x2a: port@aa000 {
cell-index = <0x2a>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xaa000 0x1000>;
};
ethernet@e4000 {
cell-index = <2>;
compatible = "fsl,fman-memac";
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy2>;
};
mdio@e5000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe5000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy2: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #3 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x0b: port@8b000 {
cell-index = <0xb>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x8b000 0x1000>;
};
fman0_tx_0x2b: port@ab000 {
cell-index = <0x2b>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xab000 0x1000>;
};
ethernet@e6000 {
cell-index = <3>;
compatible = "fsl,fman-memac";
reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy3>;
};
mdio@e7000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe7000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy3: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #4 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x0c: port@8c000 {
cell-index = <0xc>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x8c000 0x1000>;
};
fman0_tx_0x2c: port@ac000 {
cell-index = <0x2c>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xac000 0x1000>;
};
ethernet@e8000 {
cell-index = <4>;
compatible = "fsl,fman-memac";
reg = <0xe8000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy4>;
};
mdio@e9000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe9000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy4: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #5 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@400000 {
fman0_rx_0x0d: port@8d000 {
cell-index = <0xd>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x8d000 0x1000>;
};
fman0_tx_0x2d: port@ad000 {
cell-index = <0x2d>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xad000 0x1000>;
};
ethernet@ea000 {
cell-index = <5>;
compatible = "fsl,fman-memac";
reg = <0xea000 0x1000>;
fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>;
ptp-timer = <&ptp_timer0>;
pcsphy-handle = <&pcsphy5>;
};
mdio@eb000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xeb000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy5: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman0: fman@400000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
compatible = "fsl,fman";
ranges = <0 0x400000 0xfe000>;
reg = <0x400000 0xfe000>;
interrupts = <96 2 0 0>, <16 2 1 1>;
clocks = <&clockgen 3 0>;
clock-names = "fmanclk";
fsl,qman-channel-range = <0x800 0x10>;
ptimer-handle = <&ptp_timer0>;
muram@0 {
compatible = "fsl,fman-muram";
reg = <0x0 0x60000>;
};
fman0_oh_0x2: port@82000 {
cell-index = <0x2>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x82000 0x1000>;
};
fman0_oh_0x3: port@83000 {
cell-index = <0x3>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x83000 0x1000>;
};
fman0_oh_0x4: port@84000 {
cell-index = <0x4>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x84000 0x1000>;
};
fman0_oh_0x5: port@85000 {
cell-index = <0x5>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x85000 0x1000>;
};
fman0_oh_0x6: port@86000 {
cell-index = <0x6>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x86000 0x1000>;
};
fman0_oh_0x7: port@87000 {
cell-index = <0x7>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x87000 0x1000>;
};
mdio0: mdio@fc000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xfc000 0x1000>;
};
xmdio0: mdio@fd000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xfd000 0x1000>;
};
};
ptp_timer0: ptp-timer@4fe000 {
compatible = "fsl,fman-ptp-timer";
reg = <0x4fe000 0x1000>;
interrupts = <96 2 0 0>;
clocks = <&clockgen 3 0>;
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 10g port #0 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x10: port@90000 {
cell-index = <0x10>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x90000 0x1000>;
fsl,fman-10g-port;
};
fman1_tx_0x30: port@b0000 {
cell-index = <0x30>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xb0000 0x1000>;
fsl,fman-10g-port;
};
ethernet@f0000 {
cell-index = <0x8>;
compatible = "fsl,fman-memac";
reg = <0xf0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
pcsphy-handle = <&pcsphy14>;
};
mdio@f1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf1000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy14: ethernet-phy@0 {
reg = <0x0>;
};
};
};

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// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x11: port@91000 {
cell-index = <0x11>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x91000 0x1000>;
fsl,fman-10g-port;
};
fman1_tx_0x31: port@b1000 {
cell-index = <0x31>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xb1000 0x1000>;
fsl,fman-10g-port;
};
ethernet@f2000 {
cell-index = <0x9>;
compatible = "fsl,fman-memac";
reg = <0xf2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x11 &fman1_tx_0x31>;
pcsphy-handle = <&pcsphy15>;
};
mdio@f3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xf3000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy15: ethernet-phy@0 {
reg = <0x0>;
};
};
};

43
arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #0 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x08: port@88000 {
cell-index = <0x8>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x88000 0x1000>;
};
fman1_tx_0x28: port@a8000 {
cell-index = <0x28>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xa8000 0x1000>;
};
ethernet@e0000 {
cell-index = <0>;
compatible = "fsl,fman-memac";
reg = <0xe0000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x08 &fman1_tx_0x28>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy8>;
};
mdio@e1000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe1000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy8: ethernet-phy@0 {
reg = <0x0>;
};
};
};

43
arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #1 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x09: port@89000 {
cell-index = <0x9>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x89000 0x1000>;
};
fman1_tx_0x29: port@a9000 {
cell-index = <0x29>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xa9000 0x1000>;
};
ethernet@e2000 {
cell-index = <1>;
compatible = "fsl,fman-memac";
reg = <0xe2000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x09 &fman1_tx_0x29>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy9>;
};
mdio@e3000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe3000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy9: ethernet-phy@0 {
reg = <0x0>;
};
};
};

43
arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #2 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x0a: port@8a000 {
cell-index = <0xa>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x8a000 0x1000>;
};
fman1_tx_0x2a: port@aa000 {
cell-index = <0x2a>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xaa000 0x1000>;
};
ethernet@e4000 {
cell-index = <2>;
compatible = "fsl,fman-memac";
reg = <0xe4000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0a &fman1_tx_0x2a>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy10>;
};
mdio@e5000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe5000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy10: ethernet-phy@0 {
reg = <0x0>;
};
};
};

43
arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #3 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x0b: port@8b000 {
cell-index = <0xb>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x8b000 0x1000>;
};
fman1_tx_0x2b: port@ab000 {
cell-index = <0x2b>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xab000 0x1000>;
};
ethernet@e6000 {
cell-index = <3>;
compatible = "fsl,fman-memac";
reg = <0xe6000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0b &fman1_tx_0x2b>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy11>;
};
mdio@e7000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe7000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy11: ethernet-phy@0 {
reg = <0x0>;
};
};
};

43
arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #4 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x0c: port@8c000 {
cell-index = <0xc>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x8c000 0x1000>;
};
fman1_tx_0x2c: port@ac000 {
cell-index = <0x2c>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xac000 0x1000>;
};
ethernet@e8000 {
cell-index = <4>;
compatible = "fsl,fman-memac";
reg = <0xe8000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0c &fman1_tx_0x2c>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy12>;
};
mdio@e9000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xe9000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy12: ethernet-phy@0 {
reg = <0x0>;
};
};
};

43
arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi Normal file
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@ -0,0 +1,43 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 1g port #5 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman@500000 {
fman1_rx_0x0d: port@8d000 {
cell-index = <0xd>;
compatible = "fsl,fman-v3-port-rx";
reg = <0x8d000 0x1000>;
};
fman1_tx_0x2d: port@ad000 {
cell-index = <0x2d>;
compatible = "fsl,fman-v3-port-tx";
reg = <0xad000 0x1000>;
};
ethernet@ea000 {
cell-index = <5>;
compatible = "fsl,fman-memac";
reg = <0xea000 0x1000>;
fsl,fman-ports = <&fman1_rx_0x0d &fman1_tx_0x2d>;
ptp-timer = <&ptp_timer1>;
pcsphy-handle = <&pcsphy13>;
};
mdio@eb000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xeb000 0x1000>;
fsl,erratum-a011043; /* must ignore read errors */
pcsphy13: ethernet-phy@0 {
reg = <0x0>;
};
};
};

84
arch/powerpc/dts/qoriq-fman3-1.dtsi Normal file
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@ -0,0 +1,84 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 device tree stub [ controller @ offset 0x500000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman1: fman@500000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <1>;
compatible = "fsl,fman";
ranges = <0 0x500000 0xfe000>;
reg = <0x500000 0xfe000>;
interrupts = <97 2 0 0>, <16 2 1 0>;
clocks = <&clockgen 3 1>;
clock-names = "fmanclk";
fsl,qman-channel-range = <0x820 0x10>;
ptimer-handle = <&ptp_timer1>;
muram@0 {
compatible = "fsl,fman-muram";
reg = <0x0 0x60000>;
};
fman1_oh_0x2: port@82000 {
cell-index = <0x2>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x82000 0x1000>;
};
fman1_oh_0x3: port@83000 {
cell-index = <0x3>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x83000 0x1000>;
};
fman1_oh_0x4: port@84000 {
cell-index = <0x4>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x84000 0x1000>;
};
fman1_oh_0x5: port@85000 {
cell-index = <0x5>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x85000 0x1000>;
};
fman1_oh_0x6: port@86000 {
cell-index = <0x6>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x86000 0x1000>;
};
fman1_oh_0x7: port@87000 {
cell-index = <0x7>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x87000 0x1000>;
};
mdio1: mdio@fc000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xfc000 0x1000>;
};
mdio@fd000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xfd000 0x1000>;
};
};
ptp_timer1: ptp-timer@5fe000 {
compatible = "fsl,fman-ptp-timer";
reg = <0x5fe000 0x1000>;
interrupts = <97 2 0 0>;
clocks = <&clockgen 3 1>;
};

72
arch/powerpc/dts/qoriq-fman3l-0.dtsi Normal file
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@ -0,0 +1,72 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ FMan v3 device tree stub [ controller @ offset 0x400000 ]
*
* Copyright 2012 - 2015 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
fman0: fman@400000 {
#address-cells = <1>;
#size-cells = <1>;
cell-index = <0>;
compatible = "fsl,fman";
ranges = <0 0x400000 0xfe000>;
reg = <0x400000 0xfe000>;
interrupts = <96 2 0 0>, <16 2 1 1>;
clocks = <&clockgen 3 0>;
clock-names = "fmanclk";
fsl,qman-channel-range = <0x800 0x10>;
ptimer-handle = <&ptp_timer0>;
muram@0 {
compatible = "fsl,fman-muram";
reg = <0x0 0x30000>;
};
fman0_oh_0x2: port@82000 {
cell-index = <0x2>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x82000 0x1000>;
};
fman0_oh_0x3: port@83000 {
cell-index = <0x3>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x83000 0x1000>;
};
fman0_oh_0x4: port@84000 {
cell-index = <0x4>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x84000 0x1000>;
};
fman0_oh_0x5: port@85000 {
cell-index = <0x5>;
compatible = "fsl,fman-v3-port-oh";
reg = <0x85000 0x1000>;
};
mdio0: mdio@fc000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xfc000 0x1000>;
};
xmdio0: mdio@fd000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio";
reg = <0xfd000 0x1000>;
};
};
ptp_timer0: ptp-timer@4fe000 {
compatible = "fsl,fman-ptp-timer";
reg = <0x4fe000 0x1000>;
interrupts = <96 2 0 0>;
clocks = <&clockgen 3 0>;
};

16
arch/powerpc/dts/qoriq-gpio-0.dtsi Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ GPIO device tree stub [ controller @ offset 0x130000 ]
*
* Copyright 2011 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
gpio0: gpio@130000 {
compatible = "fsl,qoriq-gpio";
reg = <0x130000 0x1000>;
interrupts = <55 2 0 0>;
#gpio-cells = <2>;
gpio-controller;
};

16
arch/powerpc/dts/qoriq-gpio-1.dtsi Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ GPIO device tree stub [ controller @ offset 0x131000 ]
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
gpio1: gpio@131000 {
compatible = "fsl,qoriq-gpio";
reg = <0x131000 0x1000>;
interrupts = <54 2 0 0>;
#gpio-cells = <2>;
gpio-controller;
};

16
arch/powerpc/dts/qoriq-gpio-2.dtsi Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ GPIO device tree stub [ controller @ offset 0x132000 ]
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
gpio2: gpio@132000 {
compatible = "fsl,qoriq-gpio";
reg = <0x132000 0x1000>;
interrupts = <86 2 0 0>;
#gpio-cells = <2>;
gpio-controller;
};

16
arch/powerpc/dts/qoriq-gpio-3.dtsi Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* QorIQ GPIO device tree stub [ controller @ offset 0x133000 ]
*
* Copyright 2013 Freescale Semiconductor Inc.
* Copyright 2020 NXP
*
*/
gpio3: gpio@133000 {
compatible = "fsl,qoriq-gpio";
reg = <0x133000 0x1000>;
interrupts = <87 2 0 0>;
#gpio-cells = <2>;
gpio-controller;
};

37
arch/powerpc/dts/t1023si-post.dtsi Normal file
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@ -0,0 +1,37 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* T1023 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2014 Freescale Semiconductor Inc.
* Copyright 2019-2020 NXP
*
*/
&soc {
/include/ "qoriq-clockgen2.dtsi"
/include/ "qoriq-gpio-0.dtsi"
/include/ "qoriq-gpio-1.dtsi"
/include/ "qoriq-gpio-2.dtsi"
/include/ "qoriq-gpio-3.dtsi"
/* include used FMan blocks */
/include/ "qoriq-fman3l-0.dtsi"
/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi"
/include/ "qoriq-fman3-0-1g-1.dtsi"
/include/ "qoriq-fman3-0-1g-2.dtsi"
/include/ "qoriq-fman3-0-1g-3.dtsi"
fman@400000 {
enet0: ethernet@e0000 {
};
enet1: ethernet@e2000 {
};
enet2: ethernet@e4000 {
};
enet3: ethernet@e6000 {
};
};
};

54
arch/powerpc/dts/t1024rdb.dts
View File

@ -3,7 +3,7 @@
* T1024RDB Device Tree Source
*
* Copyright 2013 - 2015 Freescale Semiconductor Inc.
* Copyright 2019 NXP
* Copyright 2019-2020 NXP
*/
/include/ "t102x.dtsi"
@ -14,4 +14,56 @@
#address-cells = <2>;
#size-cells = <2>;
interrupt-parent = <&mpic>;
aliases {
sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
};
soc: soc@ffe000000 {
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
reg = <0xf 0xfe000000 0 0x00001000>;
fman@400000 {
fm1mac1: ethernet@e0000 {
phy-handle = <&xg_aqr105_phy3>;
phy-connection-type = "xgmii";
};
fm1mac2: ethernet@e2000 {
};
fm1mac3: ethernet@e4000 {
phy-handle = <&rgmii_phy2>;
phy-connection-type = "rgmii";
};
fm1mac4: ethernet@e6000 {
phy-handle = <&rgmii_phy1>;
phy-connection-type = "rgmii";
};
mdio0: mdio@fc000 {
rgmii_phy1: ethernet-phy@2 {
reg = <0x2>;
};
rgmii_phy2: ethernet-phy@6 {
reg = <0x6>;
};
};
xmdio0: mdio@fd000 {
xg_aqr105_phy3: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x1>;
};
sg_2500_aqr105_phy4: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c45";
reg = <0x2>;
};
};
};
};
};
#include "t1024si-post.dtsi"

10
arch/powerpc/dts/t1024si-post.dtsi Normal file
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@ -0,0 +1,10 @@
// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
* T1024 Silicon/SoC Device Tree Source (post include)
*
* Copyright 2014 Freescale Semiconductor Inc.
* Copyright 2019-2020 NXP
*
*/
#include "t1023si-post.dtsi"

3
arch/powerpc/include/asm/mpc85xx_gpio.h
View File

@ -6,6 +6,7 @@
#ifndef POWERPC_ASM_MPC85XX_GPIO_H_
#define POWERPC_ASM_MPC85XX_GPIO_H_
#ifndef CONFIG_DM_GPIO
# include <asm/immap_85xx.h>
/*
@ -110,5 +111,5 @@ static inline int gpio_is_valid(int gpio)
{
return (gpio >= 0) && (gpio < 32);
}
#endif /* not CONFIG_DM_GPIO */
#endif /* not POWERPC_ASM_MPC85XX_GPIO_H_ */

2
board/freescale/b4860qds/b4860qds.c
View File

@ -1219,7 +1219,9 @@ int ft_board_setup(void *blob, bd_t *bd)
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif

2
board/freescale/corenet_ds/corenet_ds.c
View File

@ -207,7 +207,9 @@ int ft_board_setup(void *blob, bd_t *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif

2
board/freescale/ls1043aqds/ls1043aqds.c
View File

@ -576,7 +576,9 @@ int ft_board_setup(void *blob, bd_t *bd)
ft_cpu_setup(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif

5
board/freescale/p1023rdb/p1023rdb.c
View File

@ -150,8 +150,11 @@ int ft_board_setup(void *blob, bd_t *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
#endif
return 0;
}
#endif

2
board/freescale/p2041rdb/p2041rdb.c
View File

@ -237,7 +237,9 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_liodn(blob);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
#endif
return 0;

2
board/freescale/t102xqds/t102xqds.c
View File

@ -474,7 +474,9 @@ int ft_board_setup(void *blob, bd_t *bd)
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif
fdt_fixup_spi_mux(blob);

2
board/freescale/t102xrdb/t102xrdb.c
View File

@ -203,7 +203,9 @@ int ft_board_setup(void *blob, bd_t *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif

2
board/freescale/t1040qds/t1040qds.c
View File

@ -278,7 +278,9 @@ int ft_board_setup(void *blob, bd_t *bd)
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif

2
board/freescale/t104xrdb/t104xrdb.c
View File

@ -152,7 +152,9 @@ int ft_board_setup(void *blob, bd_t *bd)
#endif
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
#endif
if (hwconfig("qe-tdm"))

2
board/freescale/t208xqds/t208xqds.c
View File

@ -481,7 +481,9 @@ int ft_board_setup(void *blob, bd_t *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif

2
board/freescale/t208xrdb/t208xrdb.c
View File

@ -134,7 +134,9 @@ int ft_board_setup(void *blob, bd_t *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif

2
board/freescale/t4qds/t4240qds.c
View File

@ -736,7 +736,9 @@ int ft_board_setup(void *blob, bd_t *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif

2
board/freescale/t4rdb/t4240rdb.c
View File

@ -113,7 +113,9 @@ int ft_board_setup(void *blob, bd_t *bd)
fsl_fdt_fixup_dr_usb(blob, bd);
#ifdef CONFIG_SYS_DPAA_FMAN
#ifndef CONFIG_DM_ETH
fdt_fixup_fman_ethernet(blob);
#endif
fdt_fixup_board_enet(blob);
#endif

3
configs/P2041RDB_NAND_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@ -49,6 +50,8 @@ CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y

3
configs/P2041RDB_SDCARD_defconfig
View File

@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@ -48,6 +49,8 @@ CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y

8
configs/P2041RDB_SECURE_BOOT_defconfig
View File

@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_P2041RDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -15,6 +15,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@ -25,7 +26,8 @@ CONFIG_CMD_PING=y
CONFIG_MP=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="p2041rdb"
CONFIG_DM=y
CONFIG_FSL_ESDHC=y
CONFIG_MTD=y
@ -41,6 +43,8 @@ CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y

3
configs/P2041RDB_SPIFLASH_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@ -49,6 +50,8 @@ CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y

3
configs/P2041RDB_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_BOARD_EARLY_INIT_R=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_DM=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_SF=y
@ -47,6 +48,8 @@ CONFIG_PHYLIB=y
CONFIG_PHYLIB_10G=y
CONFIG_PHY_TERANETICS=y
CONFIG_PHY_VITESSE=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_PHY_GIGE=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y

3
configs/T1024RDB_NAND_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_CMD_I2C=y
@ -71,6 +72,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y

3
configs/T1024RDB_SDCARD_defconfig
View File

@ -32,6 +32,7 @@ CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_CMD_I2C=y
@ -68,6 +69,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y

8
configs/T1024RDB_SECURE_BOOT_defconfig
View File

@ -4,7 +4,7 @@ CONFIG_ENV_SIZE=0x2000
CONFIG_NXP_ESBC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T1024RDB=y
# CONFIG_SYS_MALLOC_F is not set
CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
CONFIG_FIT=y
CONFIG_FIT_VERBOSE=y
CONFIG_OF_BOARD_SETUP=y
@ -19,6 +19,7 @@ CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_CMD_I2C=y
@ -34,7 +35,8 @@ CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_MTDIDS_DEFAULT="nor0=fe8000000.nor,nand0=fff800000.flash,spi0=spife110000.1"
CONFIG_MTDPARTS_DEFAULT="mtdparts=fe8000000.nor:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot),5m(kernel),128k(dtb),96m(fs),-(user);spife110000.0:1m(uboot),5m(kernel),128k(dtb),-(user)"
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="t1024rdb"
CONFIG_DM=y
CONFIG_SYS_FSL_DDR3=y
CONFIG_FSL_ESDHC=y
@ -52,6 +54,8 @@ CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_E1000=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y
CONFIG_SYS_QE_FMAN_FW_IN_NOR=y

3
configs/T1024RDB_SPIFLASH_defconfig
View File

@ -34,6 +34,7 @@ CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_CMD_I2C=y
@ -71,6 +72,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y

3
configs/T1024RDB_defconfig
View File

@ -19,6 +19,7 @@ CONFIG_CMD_IMLS=y
CONFIG_CMD_GREPENV=y
CONFIG_CMD_MEMTEST=y
CONFIG_SYS_ALT_MEMTEST=y
CONFIG_CMD_DM=y
CONFIG_SYS_MEMTEST_START=0x00200000
CONFIG_SYS_MEMTEST_END=0x00400000
CONFIG_CMD_I2C=y
@ -56,6 +57,8 @@ CONFIG_SPI_FLASH_STMICRO=y
CONFIG_PHYLIB=y
CONFIG_PHY_AQUANTIA=y
CONFIG_PHY_REALTEK=y
CONFIG_DM_ETH=y
CONFIG_DM_MDIO=y
CONFIG_E1000=y
CONFIG_FMAN_ENET=y
CONFIG_MII=y

4
doc/device-tree-bindings/net/fsl-tsec-phy.txt
View File

@ -2,7 +2,7 @@
Properties:
- compatible : Should be "fsl,tsec"
- compatible : Should be "fsl,etsec2"
- reg : Offset and length of the register set for the device
- phy-handle : See ethernet.txt file in the same directory.
- phy-connection-type : See ethernet.txt file in the same directory. This
@ -12,7 +12,7 @@ Properties:
Example:
ethernet@24000 {
compatible = "fsl,tsec";
compatible = "fsl,etsec2";
reg = <0x24000 0x1000>;
phy-handle = <&phy0>;
phy-connection-type = "sgmii";

3
drivers/ddr/fsl/Kconfig
View File

@ -151,6 +151,9 @@ endmenu
config SYS_FSL_ERRATUM_A008378
bool
config SYS_FSL_ERRATUM_A008109
bool
config SYS_FSL_ERRATUM_A008511
bool

58
drivers/ddr/fsl/ctrl_regs.c
View File

@ -1,7 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2008-2016 Freescale Semiconductor, Inc.
* Copyright 2017-2018 NXP Semiconductor
* Copyright 2017-2020 NXP Semiconductor
*/
/*
@ -2363,38 +2363,6 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
unsigned int ip_rev = 0;
unsigned int unq_mrs_en = 0;
int cs_en = 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
unsigned int ddr_freq;
#endif
#if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
defined(CONFIG_SYS_FSL_ERRATUM_A009942)
struct ccsr_ddr __iomem *ddrc;
switch (ctrl_num) {
case 0:
ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
break;
#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
case 1:
ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
case 2:
ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
break;
#endif
#if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
case 3:
ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
break;
#endif
default:
printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
return 1;
}
#endif
memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
@ -2615,31 +2583,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
ddr->debug[2] |= 0x00000200; /* set bit 22 */
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
/* Erratum applies when accumulated ECC is used, or DBI is enabled */
#define IS_ACC_ECC_EN(v) ((v) & 0x4)
#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
if (has_erratum_a008378()) {
if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
IS_DBI(ddr->ddr_sdram_cfg_3)) {
ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
ddr->debug[28] |= (0x9 << 20);
}
}
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
ddr->debug[28] &= 0xff0fff00;
if (ddr_freq <= 1333)
ddr->debug[28] |= 0x0080006a;
else if (ddr_freq <= 1600)
ddr->debug[28] |= 0x0070006f;
else if (ddr_freq <= 1867)
ddr->debug[28] |= 0x00700076;
else if (ddr_freq <= 2133)
ddr->debug[28] |= 0x0060007b;
if (popts->cpo_sample)
ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
popts->cpo_sample;

54
drivers/ddr/fsl/fsl_ddr_gen4.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015 Freescale Semiconductor, Inc.
* Copyright 2014-2020 Freescale Semiconductor, Inc.
*/
#include <common.h>
@ -72,6 +72,15 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
#endif
#ifdef CONFIG_FSL_DDR_BIST
char buffer[CONFIG_SYS_CBSIZE];
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) || \
(defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
defined(CONFIG_SYS_FSL_ERRATUM_A008109)
u32 val32;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
unsigned int ddr_freq;
#endif
switch (ctrl_num) {
case 0:
@ -437,6 +446,49 @@ step2:
ddr_out32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
/* Erratum applies when accumulated ECC is used, or DBI is enabled */
#define IS_ACC_ECC_EN(v) ((v) & 0x4)
#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
if (has_erratum_a008378()) {
if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
IS_DBI(regs->ddr_sdram_cfg_3)) {
val32 = ddr_in32(&ddr->debug[28]);
val32 |= (0x9 << 20);
ddr_out32(&ddr->debug[28], val32);
}
debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A008378\n");
}
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A008109)
val32 = ddr_in32(&ddr->sdram_cfg_2) | 0x800; /* DDR_SLOW */
ddr_out32(&ddr->sdram_cfg_2, val32);
val32 = ddr_in32(&ddr->debug[18]) | 0x2;
ddr_out32(&ddr->debug[18], val32);
ddr_out32(&ddr->debug[28], 0x30000000);
debug("Applied errta CONFIG_SYS_FSL_ERRATUM_A008109\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
val32 = ddr_in32(&ddr->debug[28]);
val32 &= 0xff0fff00;
if (ddr_freq <= 1333)
val32 |= 0x0080006a;
else if (ddr_freq <= 1600)
val32 |= 0x0070006f;
else if (ddr_freq <= 1867)
val32 |= 0x00700076;
else if (ddr_freq <= 2133)
val32 |= 0x0060007b;
ddr_out32(&ddr->debug[28], val32);
debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n");
#endif
total_gb_size_per_controller = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
if (!(regs->cs[i].config & 0x80000000))

54
drivers/ddr/fsl/mpc85xx_ddr_gen3.c
View File

@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2008-2012 Freescale Semiconductor, Inc.
* Copyright 2008-2020 Freescale Semiconductor, Inc.
*/
#include <common.h>
@ -40,6 +40,15 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
u32 save1, save2;
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) || \
(defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
defined(CONFIG_SYS_FSL_ERRATUM_A008109)
u32 val32;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
unsigned int ddr_freq;
#endif
switch (ctrl_num) {
case 0:
@ -338,6 +347,49 @@ step2:
}
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
/* Erratum applies when accumulated ECC is used, or DBI is enabled */
#define IS_ACC_ECC_EN(v) ((v) & 0x4)
#define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
if (has_erratum_a008378()) {
if (IS_ACC_ECC_EN(regs->ddr_sdram_cfg) ||
IS_DBI(regs->ddr_sdram_cfg_3)) {
val32 = ddr_in32(&ddr->debug[28]);
val32 |= (0x9 << 20);
ddr_out32(&ddr->debug[28], val32);
}
debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A008378\n");
}
#endif
#if defined(CONFIG_SYS_FSL_ERRATUM_A008109)
val32 = in_be32(&ddr->sdram_cfg_2) | 0x800; /* DDR_SLOW */
out_be32(&ddr->sdram_cfg_2, val32);
val32 = in_be32(&ddr->debug[18]) | 0x2;
out_be32(&ddr->debug[18], val32);
out_be32(&ddr->debug[28], 0x30000000);
debug("Applied errta CONFIG_SYS_FSL_ERRATUM_A008109\n");
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
val32 = in_be32(&ddr->debug[28]);
val32 &= 0xff0fff00;
if (ddr_freq <= 1333)
val32 |= 0x0080006a;
else if (ddr_freq <= 1600)
val32 |= 0x0070006f;
else if (ddr_freq <= 1867)
val32 |= 0x00700076;
else if (ddr_freq <= 2133)
val32 |= 0x0060007b;
out_be32(&ddr->debug[28], val32);
debug("Applied errata CONFIG_SYS_FSL_ERRATUM_A009942\n");
#endif
/*
* For 8572 DDR1 erratum - DDR controller may enter illegal state
* when operatiing in 32-bit bus mode with 4-beat bursts,

1
drivers/net/Kconfig
View File

@ -162,6 +162,7 @@ config DWC_ETH_QOS
config E1000
bool "Intel PRO/1000 Gigabit Ethernet support"
depends on (DM_ETH && DM_PCI) || !DM_ETH
help
This driver supports Intel(R) PRO/1000 gigabit ethernet family of
adapters. For more information on how to identify your adapter, go

140
drivers/net/fsl_mdio.c
View File

@ -12,6 +12,12 @@
#include <asm/io.h>
#include <linux/errno.h>
#ifdef CONFIG_DM_MDIO
struct tsec_mdio_priv {
struct tsec_mii_mng __iomem *regs;
};
#endif
void tsec_local_mdio_write(struct tsec_mii_mng __iomem *phyregs, int port_addr,
int dev_addr, int regnum, int value)
{
@ -56,10 +62,21 @@ int tsec_local_mdio_read(struct tsec_mii_mng __iomem *phyregs, int port_addr,
return value;
}
#if defined(CONFIG_PHYLIB)
static int fsl_pq_mdio_reset(struct mii_dev *bus)
{
struct tsec_mii_mng __iomem *regs =
(struct tsec_mii_mng __iomem *)bus->priv;
struct tsec_mii_mng __iomem *regs;
#ifndef CONFIG_DM_MDIO
regs = (struct tsec_mii_mng __iomem *)bus->priv;
#else
struct tsec_mdio_priv *priv;
if (!bus->priv)
return -EINVAL;
priv = dev_get_priv(bus->priv);
regs = priv->regs;
#endif
/* Reset MII (due to new addresses) */
out_be32(&regs->miimcfg, MIIMCFG_RESET_MGMT);
@ -71,11 +88,22 @@ static int fsl_pq_mdio_reset(struct mii_dev *bus)
return 0;
}
#endif
int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
{
struct tsec_mii_mng __iomem *phyregs =
(struct tsec_mii_mng __iomem *)bus->priv;
struct tsec_mii_mng __iomem *phyregs;
#ifndef CONFIG_DM_MDIO
phyregs = (struct tsec_mii_mng __iomem *)bus->priv;
#else
struct tsec_mdio_priv *priv;
if (!bus->priv)
return -EINVAL;
priv = dev_get_priv(bus->priv);
phyregs = priv->regs;
#endif
return tsec_local_mdio_read(phyregs, addr, dev_addr, regnum);
}
@ -83,14 +111,25 @@ int tsec_phy_read(struct mii_dev *bus, int addr, int dev_addr, int regnum)
int tsec_phy_write(struct mii_dev *bus, int addr, int dev_addr, int regnum,
u16 value)
{
struct tsec_mii_mng __iomem *phyregs =
(struct tsec_mii_mng __iomem *)bus->priv;
struct tsec_mii_mng __iomem *phyregs;
#ifndef CONFIG_DM_MDIO
phyregs = (struct tsec_mii_mng __iomem *)bus->priv;
#else
struct tsec_mdio_priv *priv;
if (!bus->priv)
return -EINVAL;
priv = dev_get_priv(bus->priv);
phyregs = priv->regs;
#endif
tsec_local_mdio_write(phyregs, addr, dev_addr, regnum, value);
return 0;
}
#ifndef CONFIG_DM_MDIO
int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
{
struct mii_dev *bus = mdio_alloc();
@ -109,3 +148,92 @@ int fsl_pq_mdio_init(bd_t *bis, struct fsl_pq_mdio_info *info)
return mdio_register(bus);
}
#else /* CONFIG_DM_MDIO */
#if defined(CONFIG_PHYLIB)
static int tsec_mdio_read(struct udevice *dev, int addr, int devad, int reg)
{
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
NULL;
if (pdata && pdata->mii_bus)
return tsec_phy_read(pdata->mii_bus, addr, devad, reg);
return -1;
}
static int tsec_mdio_write(struct udevice *dev, int addr, int devad, int reg,
u16 val)
{
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
NULL;
if (pdata && pdata->mii_bus)
return tsec_phy_write(pdata->mii_bus, addr, devad, reg, val);
return -1;
}
static int tsec_mdio_reset(struct udevice *dev)
{
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
NULL;
if (pdata && pdata->mii_bus)
return fsl_pq_mdio_reset(pdata->mii_bus);
return -1;
}
static const struct mdio_ops tsec_mdio_ops = {
.read = tsec_mdio_read,
.write = tsec_mdio_write,
.reset = tsec_mdio_reset,
};
static const struct udevice_id tsec_mdio_ids[] = {
{ .compatible = "fsl,gianfar-tbi" },
{ .compatible = "fsl,gianfar-mdio" },
{ .compatible = "fsl,etsec2-tbi" },
{ .compatible = "fsl,etsec2-mdio" },
{ .compatible = "fsl,fman-mdio" },
{}
};
static int tsec_mdio_probe(struct udevice *dev)
{
struct tsec_mdio_priv *priv = (dev) ? dev_get_priv(dev) : NULL;
struct mdio_perdev_priv *pdata = (dev) ? dev_get_uclass_priv(dev) :
NULL;
if (!dev) {
printf("%s dev = NULL\n", __func__);
return -1;
}
if (!priv) {
printf("dev_get_priv(dev %p) = NULL\n", dev);
return -1;
}
priv->regs = (void *)(uintptr_t)dev_read_addr(dev);
debug("%s priv %p @ regs %p, pdata %p\n", __func__,
priv, priv->regs, pdata);
return 0;
}
static int tsec_mdio_remove(struct udevice *dev)
{
return 0;
}
U_BOOT_DRIVER(tsec_mdio) = {
.name = "tsec_mdio",
.id = UCLASS_MDIO,
.of_match = tsec_mdio_ids,
.probe = tsec_mdio_probe,
.remove = tsec_mdio_remove,
.ops = &tsec_mdio_ops,
.priv_auto_alloc_size = sizeof(struct tsec_mdio_priv),
.platdata_auto_alloc_size = sizeof(struct mdio_perdev_priv),
};
#endif /* CONFIG_PHYLIB */
#endif /* CONFIG_DM_MDIO */

32
drivers/net/tsec.c
View File

@ -791,6 +791,7 @@ int tsec_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
struct tsec_private *priv = dev_get_priv(dev);
struct tsec_mii_mng __iomem *ext_phyregs_mii;
struct ofnode_phandle_args phandle_args;
u32 tbiaddr = CONFIG_SYS_TBIPA_VALUE;
struct fsl_pq_mdio_info mdio_info;
@ -800,7 +801,7 @@ int tsec_probe(struct udevice *dev)
int ret;
pdata->iobase = (phys_addr_t)dev_read_addr(dev);
priv->regs = (struct tsec *)pdata->iobase;
priv->regs = dev_remap_addr(dev);
if (dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
&phandle_args)) {
@ -819,14 +820,35 @@ int tsec_probe(struct udevice *dev)
}
reg = ofnode_get_addr_index(parent, 0);
priv->phyregs_sgmii = (struct tsec_mii_mng *)
(reg + TSEC_MDIO_REGS_OFFSET);
if (reg == FDT_ADDR_T_NONE) {
printf("No 'reg' property of MII for external PHY\n");
return -ENOENT;
}
ext_phyregs_mii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET, 0,
MAP_NOCACHE);
ret = dev_read_phandle_with_args(dev, "tbi-handle", NULL, 0, 0,
&phandle_args);
if (ret == 0)
if (ret == 0) {
ofnode_read_u32(phandle_args.node, "reg", &tbiaddr);
parent = ofnode_get_parent(phandle_args.node);
if (!ofnode_valid(parent)) {
printf("No parent node for TBI PHY?\n");
return -ENOENT;
}
reg = ofnode_get_addr_index(parent, 0);
if (reg == FDT_ADDR_T_NONE) {
printf("No 'reg' property of MII for TBI PHY\n");
return -ENOENT;
}
priv->phyregs_sgmii = map_physmem(reg + TSEC_MDIO_REGS_OFFSET,
0, MAP_NOCACHE);
}
priv->tbiaddr = tbiaddr;
phy_mode = dev_read_prop(dev, "phy-connection-type", NULL);
@ -843,7 +865,7 @@ int tsec_probe(struct udevice *dev)
if (priv->interface == PHY_INTERFACE_MODE_SGMII)
priv->flags |= TSEC_SGMII;
mdio_info.regs = priv->phyregs_sgmii;
mdio_info.regs = ext_phyregs_mii;
mdio_info.name = (char *)dev->name;
ret = fsl_pq_mdio_init(NULL, &mdio_info);
if (ret)

2
drivers/qe/Kconfig
View File

@ -3,7 +3,7 @@
#
config QE
bool "Enable support for QUICC Engine"
depends on PPC
depends on PPC && !DM_ETH
default y if ARCH_T1040 || ARCH_T1042 || ARCH_T1024 || ARCH_P1021 \
|| ARCH_P1025
help