mx51evk: Convert to driver model
Make the conversion to driver model as it is mandatory. Tested booting the Linux kernel from the SD card. Signed-off-by: Fabio Estevam <festevam@gmail.com>
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1f3b3e7919
commit
07fc671d7e
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@ -651,6 +651,9 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
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dtb-$(CONFIG_MX28) += \
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imx28-xea.dtb
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dtb-$(CONFIG_MX51) += \
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imx51-babbage.dtb
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dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
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imx53-qsb.dtb \
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imx53-kp.dtb \
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@ -27,13 +27,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_FSL_ESDHC_IMX
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struct fsl_esdhc_cfg esdhc_cfg[2] = {
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{MMC_SDHC1_BASE_ADDR},
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{MMC_SDHC2_BASE_ADDR},
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};
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#endif
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int dram_init(void)
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{
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/* dram_init must store complete ramsize in gd->ram_size */
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@ -64,34 +57,6 @@ static void setup_iomux_uart(void)
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imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
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}
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static void setup_iomux_fec(void)
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{
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static const iomux_v3_cfg_t fec_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_EIM_EB2__FEC_MDIO, PAD_CTL_HYS |
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PAD_CTL_PUS_22K_UP | PAD_CTL_ODE |
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PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST),
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MX51_PAD_NANDF_CS3__FEC_MDC,
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NEW_PAD_CTRL(MX51_PAD_EIM_CS3__FEC_RDATA3, MX51_PAD_CTRL_2),
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NEW_PAD_CTRL(MX51_PAD_EIM_CS2__FEC_RDATA2, MX51_PAD_CTRL_2),
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NEW_PAD_CTRL(MX51_PAD_EIM_EB3__FEC_RDATA1, MX51_PAD_CTRL_2),
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MX51_PAD_NANDF_D9__FEC_RDATA0,
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MX51_PAD_NANDF_CS6__FEC_TDATA3,
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MX51_PAD_NANDF_CS5__FEC_TDATA2,
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MX51_PAD_NANDF_CS4__FEC_TDATA1,
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MX51_PAD_NANDF_D8__FEC_TDATA0,
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MX51_PAD_NANDF_CS7__FEC_TX_EN,
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MX51_PAD_NANDF_CS2__FEC_TX_ER,
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MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB2__FEC_COL, MX51_PAD_CTRL_4),
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NEW_PAD_CTRL(MX51_PAD_NANDF_RB3__FEC_RX_CLK, MX51_PAD_CTRL_4),
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MX51_PAD_EIM_CS5__FEC_CRS,
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MX51_PAD_EIM_CS4__FEC_RX_ER,
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NEW_PAD_CTRL(MX51_PAD_NANDF_D11__FEC_RX_DV, MX51_PAD_CTRL_4),
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};
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imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
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}
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#ifdef CONFIG_MXC_SPI
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static void setup_iomux_spi(void)
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{
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@ -112,64 +77,6 @@ static void setup_iomux_spi(void)
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}
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#endif
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#ifdef CONFIG_USB_EHCI_MX5
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#define MX51EVK_USBH1_HUB_RST IMX_GPIO_NR(1, 7)
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#define MX51EVK_USBH1_STP IMX_GPIO_NR(1, 27)
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#define MX51EVK_USB_CLK_EN_B IMX_GPIO_NR(2, 1)
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#define MX51EVK_USB_PHY_RESET IMX_GPIO_NR(2, 5)
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static void setup_usb_h1(void)
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{
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static const iomux_v3_cfg_t usb_h1_pads[] = {
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MX51_PAD_USBH1_CLK__USBH1_CLK,
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MX51_PAD_USBH1_DIR__USBH1_DIR,
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MX51_PAD_USBH1_STP__USBH1_STP,
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MX51_PAD_USBH1_NXT__USBH1_NXT,
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MX51_PAD_USBH1_DATA0__USBH1_DATA0,
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MX51_PAD_USBH1_DATA1__USBH1_DATA1,
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MX51_PAD_USBH1_DATA2__USBH1_DATA2,
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MX51_PAD_USBH1_DATA3__USBH1_DATA3,
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MX51_PAD_USBH1_DATA4__USBH1_DATA4,
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MX51_PAD_USBH1_DATA5__USBH1_DATA5,
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MX51_PAD_USBH1_DATA6__USBH1_DATA6,
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MX51_PAD_USBH1_DATA7__USBH1_DATA7,
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NEW_PAD_CTRL(MX51_PAD_GPIO1_7__GPIO1_7, 0), /* H1 hub reset */
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MX51_PAD_EIM_D17__GPIO2_1,
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MX51_PAD_EIM_D21__GPIO2_5, /* PHY reset */
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};
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imx_iomux_v3_setup_multiple_pads(usb_h1_pads, ARRAY_SIZE(usb_h1_pads));
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}
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int board_ehci_hcd_init(int port)
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{
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/* Set USBH1_STP to GPIO and toggle it */
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_USBH1_STP__GPIO1_27,
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MX51_USBH_PAD_CTRL));
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gpio_direction_output(MX51EVK_USBH1_STP, 0);
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gpio_direction_output(MX51EVK_USB_PHY_RESET, 0);
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mdelay(10);
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gpio_set_value(MX51EVK_USBH1_STP, 1);
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/* Set back USBH1_STP to be function */
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imx_iomux_v3_setup_pad(MX51_PAD_USBH1_STP__USBH1_STP);
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/* De-assert USB PHY RESETB */
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gpio_set_value(MX51EVK_USB_PHY_RESET, 1);
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/* Drive USB_CLK_EN_B line low */
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gpio_direction_output(MX51EVK_USB_CLK_EN_B, 0);
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/* Reset USB hub */
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gpio_direction_output(MX51EVK_USBH1_HUB_RST, 0);
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mdelay(2);
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gpio_set_value(MX51EVK_USBH1_HUB_RST, 1);
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return 0;
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}
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#endif
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static void power_init(void)
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{
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unsigned int val;
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@ -258,6 +165,7 @@ static void power_init(void)
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_EIM_A20__GPIO2_14,
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NO_PAD_CTRL));
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gpio_request(IMX_GPIO_NR(2, 14), "gpio2_14");
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gpio_direction_output(IMX_GPIO_NR(2, 14), 0);
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udelay(500);
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@ -265,101 +173,9 @@ static void power_init(void)
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gpio_set_value(IMX_GPIO_NR(2, 14), 1);
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}
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#ifdef CONFIG_FSL_ESDHC_IMX
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int board_mmc_getcd(struct mmc *mmc)
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{
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struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
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int ret;
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_0__GPIO1_0,
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NO_PAD_CTRL));
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gpio_direction_input(IMX_GPIO_NR(1, 0));
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imx_iomux_v3_setup_pad(NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6,
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NO_PAD_CTRL));
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gpio_direction_input(IMX_GPIO_NR(1, 6));
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if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
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ret = !gpio_get_value(IMX_GPIO_NR(1, 0));
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else
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ret = !gpio_get_value(IMX_GPIO_NR(1, 6));
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return ret;
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}
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int board_mmc_init(struct bd_info *bis)
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{
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static const iomux_v3_cfg_t sd1_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_SD1_CMD__SD1_CMD, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_CLK__SD1_CLK, PAD_CTL_DSE_MAX |
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PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA0__SD1_DATA0, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA1__SD1_DATA1, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA2__SD1_DATA2, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD1_DATA3__SD1_DATA3, PAD_CTL_DSE_MAX |
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PAD_CTL_HYS | PAD_CTL_PUS_100K_DOWN | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_0__SD1_CD, PAD_CTL_HYS),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_1__SD1_WP, PAD_CTL_HYS),
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};
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static const iomux_v3_cfg_t sd2_pads[] = {
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NEW_PAD_CTRL(MX51_PAD_SD2_CMD__SD2_CMD,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD2_CLK__SD2_CLK,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD2_DATA0__SD2_DATA0,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD2_DATA1__SD2_DATA1,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD2_DATA2__SD2_DATA2,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_SD2_DATA3__SD2_DATA3,
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PAD_CTL_DSE_MAX | PAD_CTL_SRE_FAST),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_6__GPIO1_6, PAD_CTL_HYS),
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NEW_PAD_CTRL(MX51_PAD_GPIO1_5__GPIO1_5, PAD_CTL_HYS),
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};
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u32 index;
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int ret;
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esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
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esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
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for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM;
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index++) {
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switch (index) {
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case 0:
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imx_iomux_v3_setup_multiple_pads(sd1_pads,
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ARRAY_SIZE(sd1_pads));
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break;
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case 1:
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imx_iomux_v3_setup_multiple_pads(sd2_pads,
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ARRAY_SIZE(sd2_pads));
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break;
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default:
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printf("Warning: you configured more ESDHC controller"
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"(%d) as supported by the board(2)\n",
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CONFIG_SYS_FSL_ESDHC_NUM);
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return -EINVAL;
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}
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ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
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if (ret)
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return ret;
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}
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return 0;
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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setup_iomux_fec();
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#ifdef CONFIG_USB_EHCI_MX5
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setup_usb_h1();
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#endif
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setup_iomux_lcd();
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return 0;
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@ -5,15 +5,19 @@ CONFIG_NR_DRAM_BANKS=1
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CONFIG_ENV_SIZE=0x2000
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CONFIG_ENV_OFFSET=0xC0000
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CONFIG_TARGET_MX51EVK=y
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CONFIG_DM_GPIO=y
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# CONFIG_CMD_BMODE is not set
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CONFIG_DEFAULT_DEVICE_TREE="imx51-babbage"
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx51evk/imximage.cfg"
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CONFIG_USE_PREBOOT=y
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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CONFIG_CMD_DM=y
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CONFIG_CMD_FUSE=y
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CONFIG_CMD_MMC=y
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# CONFIG_CMD_PINMUX is not set
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CONFIG_CMD_SPI=y
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CONFIG_CMD_USB=y
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# CONFIG_CMD_SETEXPR is not set
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@ -22,16 +26,30 @@ CONFIG_CMD_MII=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_DATE=y
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CONFIG_CMD_FAT=y
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CONFIG_OF_CONTROL=y
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CONFIG_ENV_OVERWRITE=y
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CONFIG_ENV_IS_IN_MMC=y
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CONFIG_SYS_RELOC_GD_ENV_ADDR=y
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CONFIG_DM=y
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CONFIG_DM_MMC=y
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CONFIG_FSL_ESDHC_IMX=y
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CONFIG_MTD=y
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CONFIG_PHYLIB=y
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CONFIG_PHY_SMSC=y
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CONFIG_PHY_FIXED=y
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CONFIG_DM_ETH=y
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CONFIG_FEC_MXC=y
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CONFIG_MII=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX5=y
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CONFIG_DM_REGULATOR=y
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CONFIG_DM_REGULATOR_FIXED=y
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CONFIG_DM_REGULATOR_GPIO=y
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CONFIG_MXC_UART=y
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CONFIG_SPI=y
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CONFIG_MXC_SPI=y
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CONFIG_USB=y
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CONFIG_DM_USB=y
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CONFIG_USB_EHCI_MX5=y
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CONFIG_USB_STORAGE=y
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CONFIG_USB_HOST_ETHER=y
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@ -39,4 +57,3 @@ CONFIG_USB_ETHER_ASIX=y
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CONFIG_USB_ETHER_SMSC95XX=y
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CONFIG_SYS_WHITE_ON_BLACK=y
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CONFIG_SPLASH_SCREEN=y
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CONFIG_OF_LIBFDT=y
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@ -51,14 +51,6 @@
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#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
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#define CONFIG_SYS_FSL_ESDHC_NUM 2
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/*
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* Eth Configs
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*/
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#define CONFIG_FEC_MXC
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#define IMX_FEC_BASE FEC_BASE_ADDR
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#define CONFIG_FEC_MXC_PHYADDR 0x1F
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/* USB Configs */
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#define CONFIG_MXC_USB_PORT 1
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#define CONFIG_MXC_USB_PORTSC PORT_PTS_ULPI
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