From edd9ad81947d2136c71657be88d6cc35a56bd22f Mon Sep 17 00:00:00 2001 From: Green Wan Date: Sun, 2 May 2021 23:23:04 -0700 Subject: [PATCH 1/4] riscv: cpu: Add callback to init each core Add a callback harts_early_init() to start.S to allow different riscv hart perform setup code for each hart as early as possible. Since all the harts enter the callback, they must be able to run the same setup. Signed-off-by: Green Wan Reviewed-by: Rick Chen Reviewed-by: Bin Meng --- arch/riscv/cpu/cpu.c | 11 +++++++++++ arch/riscv/cpu/start.S | 4 ++++ 2 files changed, 15 insertions(+) diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c index 85592f5bee..296e458db4 100644 --- a/arch/riscv/cpu/cpu.c +++ b/arch/riscv/cpu/cpu.c @@ -140,3 +140,14 @@ int arch_early_init_r(void) { return riscv_cpu_probe(); } + +/** + * harts_early_init() - A callback function called by start.S to configure + * feature settings of each hart. + * + * In a multi-core system, memory access shall be careful here, it shall + * take care of race conditions. + */ +__weak void harts_early_init(void) +{ +} diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S index 8589509e01..308b0a97a5 100644 --- a/arch/riscv/cpu/start.S +++ b/arch/riscv/cpu/start.S @@ -117,6 +117,10 @@ call_board_init_f_0: mv sp, a0 #endif + /* Configure proprietary settings and customized CSRs of harts */ +call_harts_early_init: + jal harts_early_init + #ifndef CONFIG_XIP /* * Pick hart to initialize global data and run U-Boot. The other harts From bc8bbb77f74f21582b3bfd790334397757f88575 Mon Sep 17 00:00:00 2001 From: Green Wan Date: Sun, 2 May 2021 23:23:05 -0700 Subject: [PATCH 2/4] riscv: cpu: fu740: clear feature disable CSR Clear feature disable CSR to turn on all features of hart. The detail is specified at section, 'SiFive Feature Disable CSR', in user manual https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf Signed-off-by: Green Wan Reviewed-by: Sean Anderson Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- arch/riscv/cpu/fu540/spl.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c index 45657b7909..1740ef98b6 100644 --- a/arch/riscv/cpu/fu540/spl.c +++ b/arch/riscv/cpu/fu540/spl.c @@ -6,6 +6,9 @@ #include #include +#include + +#define CSR_U74_FEATURE_DISABLE 0x7c1 int spl_soc_init(void) { @@ -21,3 +24,15 @@ int spl_soc_init(void) return 0; } + +void harts_early_init(void) +{ + /* + * Feature Disable CSR + * + * Clear feature disable CSR to '0' to turn on all features for + * each core. This operation must be in M-mode. + */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) + csr_write(CSR_U74_FEATURE_DISABLE, 0); +} From 1412b8d48a920f1a4f5eac256814d25c320fb9b6 Mon Sep 17 00:00:00 2001 From: Dylan Jhong Date: Thu, 1 Apr 2021 16:48:51 +0800 Subject: [PATCH 3/4] atcspi200: Add timeout mechanism in spi_xfer() Adding timeout mechanism to avoid spi driver from stucking in the while loop in __atcspi200_spi_xfer(). Signed-off-by: Dylan Jhong Reviewed-by: Leo Yu-Chi Liang Reviewed-by: Rick Chen --- drivers/spi/atcspi200_spi.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/spi/atcspi200_spi.c b/drivers/spi/atcspi200_spi.c index 634cd56561..775b9ffc25 100644 --- a/drivers/spi/atcspi200_spi.c +++ b/drivers/spi/atcspi200_spi.c @@ -201,7 +201,7 @@ static int __atcspi200_spi_xfer(struct nds_spi_slave *ns, size_t cmd_len = ns->cmd_len; unsigned long data_len = bitlen / 8; int rf_cnt; - int ret = 0; + int ret = 0, timeout = 0; max_tran_len = ns->max_transfer_length; switch (flags) { @@ -243,11 +243,12 @@ static int __atcspi200_spi_xfer(struct nds_spi_slave *ns, ns->tran_len = tran_len; num_blks = DIV_ROUND_UP(tran_len , CHUNK_SIZE); num_bytes = (tran_len) % CHUNK_SIZE; + timeout = SPI_TIMEOUT; if(num_bytes == 0) num_bytes = CHUNK_SIZE; __atcspi200_spi_start(ns); - while (num_blks) { + while (num_blks && (timeout--)) { event = in_le32(&ns->regs->status); if ((event & TXEPTY) && (data_out)) { __nspi_espi_tx(ns, dout); @@ -269,6 +270,11 @@ static int __atcspi200_spi_xfer(struct nds_spi_slave *ns, din = (unsigned char *)din + rx_bytes; } } + + if (!timeout) { + debug("spi_xfer: %s() timeout\n", __func__); + break; + } } data_len -= tran_len; From 91e4b7516d84cefab7324765b3c8d6a909185ce2 Mon Sep 17 00:00:00 2001 From: Heinrich Schuchardt Date: Fri, 9 Apr 2021 10:48:14 +0000 Subject: [PATCH 4/4] cmd/exception: support ebreak exception on RISC-V The ebreak instruction should generate a breakpoint exception. Signed-off-by: Heinrich Schuchardt Reviewed-by: Bin Meng Reviewed-by: Rick Chen --- cmd/riscv/exception.c | 10 ++++++++++ doc/usage/exception.rst | 3 +++ 2 files changed, 13 insertions(+) diff --git a/cmd/riscv/exception.c b/cmd/riscv/exception.c index 9687cec812..7a08061d12 100644 --- a/cmd/riscv/exception.c +++ b/cmd/riscv/exception.c @@ -8,6 +8,13 @@ #include #include +static int do_ebreak(struct cmd_tbl *cmdtp, int flag, int argc, + char *const argv[]) +{ + asm volatile ("ebreak\n"); + return CMD_RET_FAILURE; +} + static int do_unaligned(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) { @@ -28,6 +35,8 @@ static int do_undefined(struct cmd_tbl *cmdtp, int flag, int argc, } static struct cmd_tbl cmd_sub[] = { + U_BOOT_CMD_MKENT(ebreak, CONFIG_SYS_MAXARGS, 1, do_ebreak, + "", ""), U_BOOT_CMD_MKENT(unaligned, CONFIG_SYS_MAXARGS, 1, do_unaligned, "", ""), U_BOOT_CMD_MKENT(undefined, CONFIG_SYS_MAXARGS, 1, do_undefined, @@ -37,6 +46,7 @@ static struct cmd_tbl cmd_sub[] = { static char exception_help_text[] = "\n" " The following exceptions are available:\n" + " ebreak - breakpoint\n" " undefined - illegal instruction\n" " unaligned - load address misaligned\n" ; diff --git a/doc/usage/exception.rst b/doc/usage/exception.rst index db1490f005..27df88bd5c 100644 --- a/doc/usage/exception.rst +++ b/doc/usage/exception.rst @@ -31,6 +31,9 @@ type **RISC-V:** + ebreak + breakpoint exception + unaligned load address misaligned