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spi: mvebu_a3700_spi: Fix clock prescale computation

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The prescaler value computation can yield wrong result if given 0x1f at
the beginning: the value is computed to be 0x20, but the maximum value
the register can hold 0x1f, so the actual stored value in this case is
0, which is obviously wrong.
Set the upper bound of the value to 0x1f with the min macro.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Marek Behún 2019-07-23 16:49:32 +02:00 committed by Jagan Teki
parent 23b93e33ad
commit 07a5cb9d3b
1 changed files with 2 additions and 3 deletions
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5
drivers/spi/mvebu_a3700_spi.c
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@ -181,10 +181,9 @@ static int mvebu_spi_set_speed(struct udevice *bus, uint hz)
data = readl(&reg->cfg);
prescale = DIV_ROUND_UP(clk_get_rate(&plat->clk), hz);
if (prescale > 0x1f)
prescale = 0x1f;
else if (prescale > 0xf)
if (prescale > 0xf)
prescale = 0x10 + (prescale + 1) / 2;
prescale = min(prescale, 0x1fu);
data &= ~MVEBU_SPI_A3700_CLK_PRESCALE_MASK;
data |= prescale & MVEBU_SPI_A3700_CLK_PRESCALE_MASK;