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https://github.com/brain-hackers/u-boot-brain
synced 2024-07-12 14:16:17 +09:00
EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
This patch adds clock structure for Exynos4x12. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
This commit is contained in:
Chander Kashyap
Minkyu Kang
parent
b189a83a08
commit
07235ef8a3
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@ -251,6 +251,282 @@ struct exynos4_clock {
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unsigned int div_iem_l1;
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};
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struct exynos4x12_clock {
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unsigned char res1[0x4200];
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unsigned int src_leftbus;
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unsigned char res2[0x1fc];
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unsigned int mux_stat_leftbus;
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unsigned char res3[0xfc];
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unsigned int div_leftbus;
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unsigned char res4[0xfc];
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unsigned int div_stat_leftbus;
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unsigned char res5[0x1fc];
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unsigned int gate_ip_leftbus;
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unsigned char res6[0x12c];
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unsigned int gate_ip_image;
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unsigned char res7[0xcc];
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unsigned int clkout_leftbus;
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unsigned int clkout_leftbus_div_stat;
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unsigned char res8[0x37f8];
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unsigned int src_rightbus;
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unsigned char res9[0x1fc];
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unsigned int mux_stat_rightbus;
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unsigned char res10[0xfc];
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unsigned int div_rightbus;
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unsigned char res11[0xfc];
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unsigned int div_stat_rightbus;
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unsigned char res12[0x1fc];
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unsigned int gate_ip_rightbus;
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unsigned char res13[0x15c];
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unsigned int gate_ip_perir;
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unsigned char res14[0x9c];
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unsigned int clkout_rightbus;
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unsigned int clkout_rightbus_div_stat;
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unsigned char res15[0x3608];
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unsigned int epll_lock;
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unsigned char res16[0xc];
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unsigned int vpll_lock;
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unsigned char res17[0xec];
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unsigned int epll_con0;
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unsigned int epll_con1;
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unsigned int epll_con2;
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unsigned char res18[0x4];
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unsigned int vpll_con0;
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unsigned int vpll_con1;
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unsigned int vpll_con2;
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unsigned char res19[0xe4];
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unsigned int src_top0;
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unsigned int src_top1;
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unsigned char res20[0x8];
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unsigned int src_cam;
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unsigned int src_tv;
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unsigned int src_mfc;
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unsigned int src_g3d;
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unsigned char res21[0x4];
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unsigned int src_lcd;
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unsigned int src_isp;
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unsigned int src_maudio;
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unsigned int src_fsys;
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unsigned char res22[0xc];
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unsigned int src_peril0;
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unsigned int src_peril1;
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unsigned int src_cam1;
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unsigned char res23[0xb4];
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unsigned int src_mask_top;
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unsigned char res24[0xc];
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unsigned int src_mask_cam;
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unsigned int src_mask_tv;
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unsigned char res25[0xc];
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unsigned int src_mask_lcd;
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unsigned int src_mask_isp;
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unsigned int src_mask_maudio;
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unsigned int src_mask_fsys;
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unsigned char res26[0xc];
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unsigned int src_mask_peril0;
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unsigned int src_mask_peril1;
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unsigned char res27[0xb8];
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unsigned int mux_stat_top0;
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unsigned int mux_stat_top1;
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unsigned char res28[0x10];
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unsigned int mux_stat_mfc;
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unsigned int mux_stat_g3d;
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unsigned char res29[0x28];
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unsigned int mux_stat_cam1;
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unsigned char res30[0xb4];
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unsigned int div_top;
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unsigned char res31[0xc];
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unsigned int div_cam;
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unsigned int div_tv;
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unsigned int div_mfc;
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unsigned int div_g3d;
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unsigned char res32[0x4];
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unsigned int div_lcd;
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unsigned int div_isp;
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unsigned int div_maudio;
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unsigned int div_fsys0;
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unsigned int div_fsys1;
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unsigned int div_fsys2;
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unsigned int div_fsys3;
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unsigned int div_peril0;
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unsigned int div_peril1;
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unsigned int div_peril2;
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unsigned int div_peril3;
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unsigned int div_peril4;
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unsigned int div_peril5;
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unsigned int div_cam1;
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unsigned char res33[0x14];
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unsigned int div2_ratio;
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unsigned char res34[0x8c];
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unsigned int div_stat_top;
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unsigned char res35[0xc];
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unsigned int div_stat_cam;
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unsigned int div_stat_tv;
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unsigned int div_stat_mfc;
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unsigned int div_stat_g3d;
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unsigned char res36[0x4];
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unsigned int div_stat_lcd;
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unsigned int div_stat_isp;
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unsigned int div_stat_maudio;
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unsigned int div_stat_fsys0;
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unsigned int div_stat_fsys1;
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unsigned int div_stat_fsys2;
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unsigned int div_stat_fsys3;
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unsigned int div_stat_peril0;
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unsigned int div_stat_peril1;
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unsigned int div_stat_peril2;
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unsigned int div_stat_peril3;
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unsigned int div_stat_peril4;
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unsigned int div_stat_peril5;
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unsigned int div_stat_cam1;
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unsigned char res37[0x14];
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unsigned int div2_stat;
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unsigned char res38[0x29c];
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unsigned int gate_ip_cam;
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unsigned int gate_ip_tv;
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unsigned int gate_ip_mfc;
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unsigned int gate_ip_g3d;
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unsigned char res39[0x4];
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unsigned int gate_ip_lcd;
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unsigned int gate_ip_isp;
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unsigned char res40[0x4];
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unsigned int gate_ip_fsys;
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unsigned char res41[0x8];
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unsigned int gate_ip_gps;
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unsigned int gate_ip_peril;
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unsigned char res42[0xc];
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unsigned char res43[0x4];
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unsigned char res44[0xc];
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unsigned int gate_block;
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unsigned char res45[0x8c];
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unsigned int clkout_cmu_top;
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unsigned int clkout_cmu_top_div_stat;
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unsigned char res46[0x3600];
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unsigned int mpll_lock;
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unsigned char res47[0xfc];
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unsigned int mpll_con0;
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unsigned int mpll_con1;
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unsigned char res48[0xf0];
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unsigned int src_dmc;
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unsigned char res49[0xfc];
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unsigned int src_mask_dmc;
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unsigned char res50[0xfc];
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unsigned int mux_stat_dmc;
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unsigned char res51[0xfc];
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unsigned int div_dmc0;
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unsigned int div_dmc1;
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unsigned char res52[0xf8];
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unsigned int div_stat_dmc0;
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unsigned int div_stat_dmc1;
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unsigned char res53[0xf8];
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unsigned int gate_bus_dmc0;
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unsigned int gate_bus_dmc1;
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unsigned char res54[0x1f8];
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unsigned int gate_ip_dmc0;
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unsigned int gate_ip_dmc1;
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unsigned char res55[0xf8];
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unsigned int clkout_cmu_dmc;
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unsigned int clkout_cmu_dmc_div_stat;
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unsigned char res56[0x5f8];
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unsigned int dcgidx_map0;
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unsigned int dcgidx_map1;
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unsigned int dcgidx_map2;
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unsigned char res57[0x14];
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unsigned int dcgperf_map0;
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unsigned int dcgperf_map1;
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unsigned char res58[0x18];
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unsigned int dvcidx_map;
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unsigned char res59[0x1c];
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unsigned int freq_cpu;
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unsigned int freq_dpm;
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unsigned char res60[0x18];
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unsigned int dvsemclk_en;
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unsigned int maxperf;
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unsigned char res61[0x8];
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unsigned int dmc_freq_ctrl;
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unsigned int dmc_pause_ctrl;
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unsigned int dddrphy_lock_ctrl;
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unsigned int c2c_state;
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unsigned char res62[0x2f60];
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unsigned int apll_lock;
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unsigned char res63[0x8];
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unsigned char res64[0xf4];
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unsigned int apll_con0;
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unsigned int apll_con1;
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unsigned char res65[0xf8];
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unsigned int src_cpu;
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unsigned char res66[0x1fc];
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unsigned int mux_stat_cpu;
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unsigned char res67[0xfc];
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unsigned int div_cpu0;
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unsigned int div_cpu1;
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unsigned char res68[0xf8];
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unsigned int div_stat_cpu0;
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unsigned int div_stat_cpu1;
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unsigned char res69[0x2f8];
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unsigned int clk_gate_ip_cpu;
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unsigned char res70[0xfc];
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unsigned int clkout_cmu_cpu;
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unsigned int clkout_cmu_cpu_div_stat;
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unsigned char res71[0x5f8];
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unsigned int armclk_stopctrl;
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unsigned int atclk_stopctrl;
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unsigned char res72[0x10];
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unsigned char res73[0x8];
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unsigned int pwr_ctrl;
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unsigned int pwr_ctrl2;
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unsigned char res74[0xd8];
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unsigned int apll_con0_l8;
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unsigned int apll_con0_l7;
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unsigned int apll_con0_l6;
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unsigned int apll_con0_l5;
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unsigned int apll_con0_l4;
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unsigned int apll_con0_l3;
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unsigned int apll_con0_l2;
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unsigned int apll_con0_l1;
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unsigned int iem_control;
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unsigned char res75[0xdc];
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unsigned int apll_con1_l8;
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unsigned int apll_con1_l7;
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unsigned int apll_con1_l6;
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unsigned int apll_con1_l5;
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unsigned int apll_con1_l4;
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unsigned int apll_con1_l3;
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unsigned int apll_con1_l2;
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unsigned int apll_con1_l1;
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unsigned char res76[0xe0];
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unsigned int div_iem_l8;
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unsigned int div_iem_l7;
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unsigned int div_iem_l6;
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unsigned int div_iem_l5;
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unsigned int div_iem_l4;
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unsigned int div_iem_l3;
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unsigned int div_iem_l2;
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unsigned int div_iem_l1;
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unsigned char res77[0xe0];
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unsigned int l2_status;
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unsigned char res78[0xc];
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unsigned int cpu_status;
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unsigned char res79[0xc];
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unsigned int ptm_status;
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unsigned char res80[0x2edc];
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unsigned int div_isp0;
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unsigned int div_isp1;
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unsigned char res81[0xf8];
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unsigned int div_stat_isp0;
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unsigned int div_stat_isp1;
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unsigned char res82[0x3f8];
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unsigned int gate_ip_isp0;
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unsigned int gate_ip_isp1;
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unsigned char res83[0x1f8];
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unsigned int clkout_cmu_isp;
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unsigned int clkout_cmu_ispd_div_stat;
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unsigned char res84[0xf8];
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unsigned int cmu_isp_spar0;
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unsigned int cmu_isp_spar1;
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unsigned int cmu_isp_spar2;
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unsigned int cmu_isp_spar3;
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};
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struct exynos5_clock {
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unsigned int apll_lock;
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unsigned char res1[0xfc];
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