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https://github.com/brain-hackers/u-boot-brain
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x86: ich-spi: Convert driver to spi-mem ops
With the introduction of the new spi-mem model operations changed slightly. The new spi-mem operations make things a bit easier to handle for ich-spi flash interface. This patch converts the ich-spi driver by using spi-mem operations. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested on Intel CrownBay and MinnowMax Tested-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fix compiler warnings when building the driver for 64-bit] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Bernhard Messerklinger
Bin Meng
parent
fd95e10178
commit
0709ddb68f
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@ -14,6 +14,8 @@
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#include <pci_ids.h>
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#include <spi.h>
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#include <asm/io.h>
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#include <spi-mem.h>
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#include <div64.h>
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#include "ich.h"
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@ -171,18 +173,6 @@ static int ich_init_controller(struct udevice *dev,
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return 0;
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}
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static inline void spi_use_out(struct spi_trans *trans, unsigned bytes)
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{
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trans->out += bytes;
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trans->bytesout -= bytes;
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}
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static inline void spi_use_in(struct spi_trans *trans, unsigned bytes)
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{
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trans->in += bytes;
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trans->bytesin -= bytes;
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}
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static void spi_lock_down(struct ich_spi_platdata *plat, void *sbase)
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{
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if (plat->ich_version == ICHV_7) {
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@ -213,47 +203,12 @@ static bool spi_lock_status(struct ich_spi_platdata *plat, void *sbase)
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return lock != 0;
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}
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static void spi_setup_type(struct spi_trans *trans, int data_bytes)
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{
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trans->type = 0xFF;
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/* Try to guess spi type from read/write sizes */
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if (trans->bytesin == 0) {
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if (trans->bytesout + data_bytes > 4)
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/*
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* If bytesin = 0 and bytesout > 4, we presume this is
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* a write data operation, which is accompanied by an
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* address.
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*/
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trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
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else
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trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
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return;
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}
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if (trans->bytesout == 1) { /* and bytesin is > 0 */
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trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
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return;
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}
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if (trans->bytesout == 4) /* and bytesin is > 0 */
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
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/* Fast read command is called with 5 bytes instead of 4 */
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if (trans->out[0] == SPI_OPCODE_FAST_READ && trans->bytesout == 5) {
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
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--trans->bytesout;
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}
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}
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static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
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bool lock)
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{
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uint16_t optypes;
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uint8_t opmenu[ctlr->menubytes];
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trans->opcode = trans->out[0];
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spi_use_out(trans, 1);
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if (!lock) {
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/* The lock is off, so just use index 0. */
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ich_writeb(ctlr, trans->opcode, ctlr->opmenu);
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@ -285,12 +240,7 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
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optypes = ich_readw(ctlr, ctlr->optype);
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optype = (optypes >> (opcode_index * 2)) & 0x3;
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if (trans->type == SPI_OPCODE_TYPE_WRITE_NO_ADDRESS &&
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optype == SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS &&
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trans->bytesout >= 3) {
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/* We guessed wrong earlier. Fix it up. */
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trans->type = optype;
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}
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if (optype != trans->type) {
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printf("ICH SPI: Transaction doesn't fit type %d\n",
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optype);
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@ -300,26 +250,6 @@ static int spi_setup_opcode(struct ich_spi_priv *ctlr, struct spi_trans *trans,
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}
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}
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static int spi_setup_offset(struct spi_trans *trans)
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{
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/* Separate the SPI address and data */
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switch (trans->type) {
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case SPI_OPCODE_TYPE_READ_NO_ADDRESS:
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case SPI_OPCODE_TYPE_WRITE_NO_ADDRESS:
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return 0;
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case SPI_OPCODE_TYPE_READ_WITH_ADDRESS:
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case SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS:
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trans->offset = ((uint32_t)trans->out[0] << 16) |
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((uint32_t)trans->out[1] << 8) |
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((uint32_t)trans->out[2] << 0);
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spi_use_out(trans, 3);
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return 1;
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default:
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printf("Unrecognized SPI transaction type %#x\n", trans->type);
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return -EPROTO;
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}
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}
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/*
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* Wait for up to 6s til status register bit(s) turn 1 (in case wait_til_set
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* below is true) or 0. In case the wait was for the bit(s) to set - write
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@ -350,7 +280,7 @@ static int ich_status_poll(struct ich_spi_priv *ctlr, u16 bitmask,
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return -ETIMEDOUT;
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}
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void ich_spi_config_opcode(struct udevice *dev)
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static void ich_spi_config_opcode(struct udevice *dev)
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{
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struct ich_spi_priv *ctlr = dev_get_priv(dev);
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@ -365,90 +295,38 @@ void ich_spi_config_opcode(struct udevice *dev)
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ich_writel(ctlr, SPI_OPMENU_UPPER, ctlr->opmenu + sizeof(u32));
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}
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static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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static int ich_spi_exec_op(struct spi_slave *slave, const struct spi_mem_op *op)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct udevice *bus = dev_get_parent(slave->dev);
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struct ich_spi_platdata *plat = dev_get_platdata(bus);
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struct ich_spi_priv *ctlr = dev_get_priv(bus);
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uint16_t control;
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int16_t opcode_index;
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int with_address;
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int status;
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int bytes = bitlen / 8;
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struct spi_trans *trans = &ctlr->trans;
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unsigned type = flags & (SPI_XFER_BEGIN | SPI_XFER_END);
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int using_cmd = 0;
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bool lock = spi_lock_status(plat, ctlr->base);
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int ret;
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int ret = 0;
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/* We don't support writing partial bytes */
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if (bitlen % 8) {
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debug("ICH SPI: Accessing partial bytes not supported\n");
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return -EPROTONOSUPPORT;
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}
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trans->in = NULL;
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trans->out = NULL;
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trans->type = 0xFF;
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/* An empty end transaction can be ignored */
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if (type == SPI_XFER_END && !dout && !din)
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return 0;
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if (type & SPI_XFER_BEGIN)
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memset(trans, '\0', sizeof(*trans));
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/* Dp we need to come back later to finish it? */
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if (dout && type == SPI_XFER_BEGIN) {
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if (bytes > ICH_MAX_CMD_LEN) {
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debug("ICH SPI: Command length limit exceeded\n");
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return -ENOSPC;
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if (op->data.nbytes) {
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if (op->data.dir == SPI_MEM_DATA_IN) {
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trans->in = op->data.buf.in;
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trans->bytesin = op->data.nbytes;
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} else {
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trans->out = op->data.buf.out;
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trans->bytesout = op->data.nbytes;
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}
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memcpy(trans->cmd, dout, bytes);
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trans->cmd_len = bytes;
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debug_trace("ICH SPI: Saved %d bytes\n", bytes);
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}
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if (trans->opcode != op->cmd.opcode)
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trans->opcode = op->cmd.opcode;
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if (lock && trans->opcode == SPI_OPCODE_WRDIS)
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return 0;
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}
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/*
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* We process a 'middle' spi_xfer() call, which has no
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* SPI_XFER_BEGIN/END, as an independent transaction as if it had
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* an end. We therefore repeat the command. This is because ICH
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* seems to have no support for this, or because interest (in digging
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* out the details and creating a special case in the code) is low.
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*/
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if (trans->cmd_len) {
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trans->out = trans->cmd;
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trans->bytesout = trans->cmd_len;
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using_cmd = 1;
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debug_trace("ICH SPI: Using %d bytes\n", trans->cmd_len);
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} else {
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trans->out = dout;
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trans->bytesout = dout ? bytes : 0;
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}
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trans->in = din;
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trans->bytesin = din ? bytes : 0;
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/* There has to always at least be an opcode */
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if (!trans->bytesout) {
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debug("ICH SPI: No opcode for transfer\n");
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return -EPROTO;
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}
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ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
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if (ret < 0)
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return ret;
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if (plat->ich_version == ICHV_7)
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ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
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else
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ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
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spi_setup_type(trans, using_cmd ? bytes : 0);
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opcode_index = spi_setup_opcode(ctlr, trans, lock);
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if (opcode_index < 0)
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return -EINVAL;
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with_address = spi_setup_offset(trans);
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if (with_address < 0)
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return -EINVAL;
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if (trans->opcode == SPI_OPCODE_WREN) {
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/*
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@ -461,6 +339,40 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
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return 0;
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}
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ret = ich_status_poll(ctlr, SPIS_SCIP, 0);
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if (ret < 0)
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return ret;
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if (plat->ich_version == ICHV_7)
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ich_writew(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
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else
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ich_writeb(ctlr, SPIS_CDS | SPIS_FCERR, ctlr->status);
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/* Try to guess spi transaction type */
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if (op->data.dir == SPI_MEM_DATA_OUT) {
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if (op->addr.nbytes)
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trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
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else
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trans->type = SPI_OPCODE_TYPE_WRITE_NO_ADDRESS;
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} else {
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if (op->addr.nbytes)
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trans->type = SPI_OPCODE_TYPE_READ_WITH_ADDRESS;
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else
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trans->type = SPI_OPCODE_TYPE_READ_NO_ADDRESS;
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}
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/* Special erase case handling */
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if (op->addr.nbytes && !op->data.buswidth)
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trans->type = SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS;
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opcode_index = spi_setup_opcode(ctlr, trans, lock);
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if (opcode_index < 0)
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return -EINVAL;
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if (op->addr.nbytes) {
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trans->offset = op->addr.val;
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with_address = 1;
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}
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if (ctlr->speed && ctlr->max_speed >= 33000000) {
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int byte;
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@ -472,13 +384,6 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
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ich_writeb(ctlr, byte, ctlr->speed);
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}
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/* See if we have used up the command data */
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if (using_cmd && dout && bytes) {
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trans->out = dout;
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trans->bytesout = bytes;
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debug_trace("ICH SPI: Moving to data, %d bytes\n", bytes);
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}
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/* Preset control fields */
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control = SPIC_SCGO | ((opcode_index & 0x07) << 4);
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@ -513,22 +418,6 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
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return 0;
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}
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/*
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* Check if this is a write command atempting to transfer more bytes
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* than the controller can handle. Iterations for writes are not
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* supported here because each SPI write command needs to be preceded
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* and followed by other SPI commands, and this sequence is controlled
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* by the SPI chip driver.
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*/
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if (trans->bytesout > ctlr->databytes) {
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debug("ICH SPI: Too much to write. This should be prevented by the driver's max_write_size?\n");
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return -EPROTO;
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}
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/*
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* Read or write up to databytes bytes at a time until everything has
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* been sent.
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*/
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while (trans->bytesout || trans->bytesin) {
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uint32_t data_length;
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@ -543,9 +432,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
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/* Program data into FDATA0 to N */
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if (trans->bytesout) {
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write_reg(ctlr, trans->out, ctlr->data, data_length);
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spi_use_out(trans, data_length);
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if (with_address)
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trans->offset += data_length;
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trans->bytesout -= data_length;
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}
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/* Add proper control fields' values */
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@ -568,9 +455,7 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
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if (trans->bytesin) {
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read_reg(ctlr, ctlr->data, trans->in, data_length);
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spi_use_in(trans, data_length);
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if (with_address)
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trans->offset += data_length;
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trans->bytesin -= data_length;
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}
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}
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@ -581,6 +466,40 @@ static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
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return 0;
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}
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static int ich_spi_adjust_size(struct spi_slave *slave, struct spi_mem_op *op)
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{
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unsigned int page_offset;
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int addr = op->addr.val;
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unsigned int byte_count = op->data.nbytes;
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if (hweight32(ICH_BOUNDARY) == 1) {
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page_offset = addr & (ICH_BOUNDARY - 1);
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} else {
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u64 aux = addr;
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page_offset = do_div(aux, ICH_BOUNDARY);
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}
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if (op->data.dir == SPI_MEM_DATA_IN && slave->max_read_size) {
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op->data.nbytes = min(ICH_BOUNDARY - page_offset,
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slave->max_read_size);
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} else if (slave->max_write_size) {
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op->data.nbytes = min(ICH_BOUNDARY - page_offset,
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slave->max_write_size);
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}
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op->data.nbytes = min(op->data.nbytes, byte_count);
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return 0;
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}
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static int ich_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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printf("ICH SPI: Only supports memory operations\n");
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return -1;
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}
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static int ich_spi_probe(struct udevice *dev)
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{
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struct ich_spi_platdata *plat = dev_get_platdata(dev);
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@ -686,10 +605,17 @@ static int ich_spi_ofdata_to_platdata(struct udevice *dev)
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return ret;
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}
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static const struct spi_controller_mem_ops ich_controller_mem_ops = {
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.adjust_op_size = ich_spi_adjust_size,
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.supports_op = NULL,
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.exec_op = ich_spi_exec_op,
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};
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static const struct dm_spi_ops ich_spi_ops = {
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.xfer = ich_spi_xfer,
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.set_speed = ich_spi_set_speed,
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.set_mode = ich_spi_set_mode,
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.mem_ops = &ich_controller_mem_ops,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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@ -100,13 +100,8 @@ enum {
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HSFC_FSMIE = 0x8000
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};
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enum {
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ICH_MAX_CMD_LEN = 5,
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};
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struct spi_trans {
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uint8_t cmd[ICH_MAX_CMD_LEN];
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int cmd_len;
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uint8_t cmd;
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const uint8_t *out;
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uint32_t bytesout;
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uint8_t *in;
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@ -166,6 +161,8 @@ struct spi_trans {
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#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
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(SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
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#define ICH_BOUNDARY 0x1000
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enum ich_version {
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ICHV_7,
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ICHV_9,
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