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ddr: altera: sdram: Clean up set_sdr_ctrlcfg()
Get rid of the constant clrsetbits_le32(), instead prepare the whole content of the register once and write it at the end of the function. The big plan here is to remove all the CONFIG_HPS_SDR_ macros, hide them in QTS compatibility layer in board implementation and pass only a small structure into the driver. Signed-off-by: Marek Vasut <marex@denx.de>
This commit is contained in:
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f36716971d
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067c853fe6
@ -254,18 +254,29 @@ static unsigned sdram_write_verify(unsigned int *addr, unsigned reg_value)
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static void set_sdr_ctrlcfg(void)
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static void set_sdr_ctrlcfg(void)
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{
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{
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int addrorder;
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u32 addrorder;
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u32 ctrl_cfg =
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
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SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
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SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
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SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
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SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
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SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
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SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
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SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) |
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(CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
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SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
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debug("\nConfiguring CTRLCFG\n");
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debug("\nConfiguring CTRLCFG\n");
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clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK,
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE <<
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SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB);
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clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_MEMBL_MASK,
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL <<
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SDR_CTRLGRP_CTRLCFG_MEMBL_LSB);
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/*
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/* SDRAM Failure When Accessing Non-Existent Memory
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* SDRAM Failure When Accessing Non-Existent Memory
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* Set the addrorder field of the SDRAM control register
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* Set the addrorder field of the SDRAM control register
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* based on the CSBITs setting.
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* based on the CSBITs setting.
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*/
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*/
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@ -273,46 +284,21 @@ static void set_sdr_ctrlcfg(void)
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case 1:
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case 1:
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addrorder = 0; /* chip, row, bank, column */
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addrorder = 0; /* chip, row, bank, column */
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if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
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if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 0)
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debug("INFO: Changing address order to 0 (chip, row, \
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debug("INFO: Changing address order to 0 (chip, row, bank, column)\n");
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bank, column)\n");
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break;
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break;
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case 2:
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case 2:
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addrorder = 2; /* row, chip, bank, column */
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addrorder = 2; /* row, chip, bank, column */
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if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
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if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER != 2)
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debug("INFO: Changing address order to 2 (row, chip, \
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debug("INFO: Changing address order to 2 (row, chip, bank, column)\n");
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bank, column)\n");
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break;
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break;
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default:
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default:
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addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
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addrorder = CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER;
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break;
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break;
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}
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}
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clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK,
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ctrl_cfg |= addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB;
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addrorder << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB);
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clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCEN_MASK,
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writel(ctrl_cfg, &sdr_ctrl->ctrl_cfg);
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN <<
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SDR_CTRLGRP_CTRLCFG_ECCEN_LSB);
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clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK,
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN <<
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SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB);
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clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK,
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN <<
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SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB);
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clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK,
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT <<
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SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB);
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clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK,
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN <<
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SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB);
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clrsetbits_le32(&sdr_ctrl->ctrl_cfg, SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK,
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CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS <<
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SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB);
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}
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}
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static void set_sdr_dram_timing1(void)
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static void set_sdr_dram_timing1(void)
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