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powerpc: mpc85xx: Move CONFIG_FSL_LAW to Kconfig
Some header files have this macro defined conditionally and redefined unconditionally. Remove all existing definitions. Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
parent
c6e6bda3a8
commit
05cb79a72c
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@ -323,117 +323,159 @@ endchoice
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config ARCH_B4420
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config ARCH_B4420
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bool
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bool
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select FSL_LAW
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config ARCH_B4860
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config ARCH_B4860
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bool
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bool
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select FSL_LAW
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config ARCH_BSC9131
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config ARCH_BSC9131
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bool
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bool
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select FSL_LAW
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config ARCH_BSC9132
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config ARCH_BSC9132
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bool
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bool
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select FSL_LAW
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config ARCH_C29X
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config ARCH_C29X
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bool
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bool
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select FSL_LAW
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config ARCH_MPC8536
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config ARCH_MPC8536
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bool
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bool
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select FSL_LAW
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config ARCH_MPC8540
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config ARCH_MPC8540
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bool
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bool
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select FSL_LAW
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config ARCH_MPC8541
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config ARCH_MPC8541
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bool
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bool
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select FSL_LAW
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config ARCH_MPC8544
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config ARCH_MPC8544
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bool
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bool
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select FSL_LAW
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config ARCH_MPC8548
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config ARCH_MPC8548
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bool
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bool
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select FSL_LAW
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config ARCH_MPC8555
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config ARCH_MPC8555
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bool
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bool
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select FSL_LAW
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config ARCH_MPC8560
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config ARCH_MPC8560
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bool
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bool
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select FSL_LAW
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config ARCH_MPC8568
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config ARCH_MPC8568
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bool
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bool
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select FSL_LAW
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config ARCH_MPC8569
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config ARCH_MPC8569
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bool
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bool
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select FSL_LAW
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config ARCH_MPC8572
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config ARCH_MPC8572
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bool
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bool
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select FSL_LAW
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config ARCH_P1010
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config ARCH_P1010
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bool
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bool
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select FSL_LAW
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config ARCH_P1011
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config ARCH_P1011
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bool
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bool
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select FSL_LAW
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config ARCH_P1020
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config ARCH_P1020
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bool
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bool
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select FSL_LAW
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config ARCH_P1021
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config ARCH_P1021
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bool
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bool
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select FSL_LAW
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config ARCH_P1022
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config ARCH_P1022
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bool
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bool
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select FSL_LAW
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config ARCH_P1023
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config ARCH_P1023
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bool
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bool
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select FSL_LAW
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config ARCH_P1024
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config ARCH_P1024
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bool
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bool
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select FSL_LAW
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config ARCH_P1025
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config ARCH_P1025
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bool
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bool
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select FSL_LAW
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config ARCH_P2020
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config ARCH_P2020
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bool
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bool
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select FSL_LAW
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config ARCH_P2041
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config ARCH_P2041
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bool
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bool
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select FSL_LAW
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config ARCH_P3041
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config ARCH_P3041
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bool
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bool
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select FSL_LAW
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config ARCH_P4080
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config ARCH_P4080
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bool
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bool
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select FSL_LAW
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config ARCH_P5020
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config ARCH_P5020
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bool
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bool
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select FSL_LAW
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config ARCH_P5040
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config ARCH_P5040
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bool
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bool
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select FSL_LAW
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config ARCH_QEMU_E500
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config ARCH_QEMU_E500
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bool
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bool
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config ARCH_T1023
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config ARCH_T1023
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bool
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bool
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select FSL_LAW
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config ARCH_T1024
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config ARCH_T1024
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bool
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bool
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select FSL_LAW
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config ARCH_T1040
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config ARCH_T1040
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bool
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bool
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select FSL_LAW
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config ARCH_T1042
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config ARCH_T1042
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bool
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bool
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select FSL_LAW
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config ARCH_T2080
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config ARCH_T2080
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bool
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bool
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select FSL_LAW
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config ARCH_T2081
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config ARCH_T2081
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bool
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bool
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select FSL_LAW
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config ARCH_T4160
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config ARCH_T4160
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bool
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bool
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select FSL_LAW
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config ARCH_T4240
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config ARCH_T4240
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bool
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bool
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select FSL_LAW
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config FSL_LAW
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bool
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help
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Use Freescale common code for Local Access Window
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config SECURE_BOOT
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config SECURE_BOOT
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bool "Secure Boot"
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bool "Secure Boot"
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@ -19,7 +19,6 @@
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#else
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#else
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x00201000
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#define CONFIG_SYS_TEXT_BASE 0x00201000
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
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#define CONFIG_SPL_PAD_TO 0x40000
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#define CONFIG_SPL_PAD_TO 0x40000
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@ -80,8 +79,6 @@
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_SRIO_PCIE_BOOT_MASTER
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#endif
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#endif
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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/* I2C bus multiplexer */
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/* I2C bus multiplexer */
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#define I2C_MUX_PCA_ADDR 0x77
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#define I2C_MUX_PCA_ADDR 0x77
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@ -51,7 +51,6 @@
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#define CONFIG_FSL_IFC /* Enable IFC Support */
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#define CONFIG_FSL_IFC /* Enable IFC Support */
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#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
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#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_TSEC_ENET
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#define CONFIG_TSEC_ENET
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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@ -103,7 +103,6 @@
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#define CONFIG_DOS_PARTITION
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#define CONFIG_DOS_PARTITION
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#endif
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#endif
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_TSEC_ENET /* ethernet */
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#define CONFIG_TSEC_ENET /* ethernet */
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@ -102,7 +102,6 @@
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#define CONFIG_DOS_PARTITION
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#define CONFIG_DOS_PARTITION
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#endif
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#endif
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_TSEC_ENET
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#define CONFIG_TSEC_ENET
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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@ -51,7 +51,6 @@
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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/*
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/*
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* sysclk for MPC85xx
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* sysclk for MPC85xx
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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#define CONFIG_FSL_VIA
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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#define CONFIG_FSL_VIA
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_FSL_VIA
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#define CONFIG_FSL_VIA
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
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#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
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#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
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/*
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/*
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_QE /* Enable QE */
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#define CONFIG_QE /* Enable QE */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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extern unsigned long get_clock_freq(void);
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extern unsigned long get_clock_freq(void);
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_QE /* Enable QE */
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#define CONFIG_QE /* Enable QE */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#ifndef __ASSEMBLY__
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#ifndef __ASSEMBLY__
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extern unsigned long get_clock_freq(void);
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extern unsigned long get_clock_freq(void);
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
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#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_TSEC_ENET /* tsec ethernet support */
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SPL_MMC_MINIMAL
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#define CONFIG_SPL_MMC_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SPL_TEXT_BASE 0xD0001000
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#define CONFIG_SPL_TEXT_BASE 0xD0001000
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#define CONFIG_SPL_PAD_TO 0x18000
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#define CONFIG_SPL_PAD_TO 0x18000
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#define CONFIG_SPL_SPI_FLASH_MINIMAL
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#define CONFIG_SPL_SPI_FLASH_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SPL_TEXT_BASE 0xD0001000
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#define CONFIG_SPL_TEXT_BASE 0xD0001000
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#define CONFIG_SPL_PAD_TO 0x18000
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#define CONFIG_SPL_PAD_TO 0x18000
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#define CONFIG_DOS_PARTITION
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#define CONFIG_DOS_PARTITION
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#endif
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#endif
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_TSEC_ENET
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#define CONFIG_TSEC_ENET
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_ENV_OVERWRITE
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#define CONFIG_SPL_MMC_MINIMAL
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#define CONFIG_SPL_MMC_MINIMAL
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_FLUSH_IMAGE
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_FSL_LAW /* Use common FSL init code */
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SYS_TEXT_BASE 0x11001000
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_TEXT_BASE 0xf8f81000
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#define CONFIG_SPL_PAD_TO 0x20000
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#define CONFIG_SPL_PAD_TO 0x20000
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||||||
#define CONFIG_SPL_SPI_FLASH_MINIMAL
|
#define CONFIG_SPL_SPI_FLASH_MINIMAL
|
||||||
#define CONFIG_SPL_FLUSH_IMAGE
|
#define CONFIG_SPL_FLUSH_IMAGE
|
||||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x11001000
|
#define CONFIG_SYS_TEXT_BASE 0x11001000
|
||||||
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
|
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
|
||||||
#define CONFIG_SPL_PAD_TO 0x20000
|
#define CONFIG_SPL_PAD_TO 0x20000
|
||||||
|
@ -115,8 +113,6 @@
|
||||||
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
|
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
|
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
|
||||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
|
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
|
||||||
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
|
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
|
||||||
|
|
|
@ -35,7 +35,6 @@
|
||||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||||
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
||||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
|
|
||||||
#ifndef __ASSEMBLY__
|
#ifndef __ASSEMBLY__
|
||||||
extern unsigned long get_clock_freq(void);
|
extern unsigned long get_clock_freq(void);
|
||||||
|
|
|
@ -58,8 +58,6 @@
|
||||||
#define CONFIG_SRIO_PCIE_BOOT_MASTER
|
#define CONFIG_SRIO_PCIE_BOOT_MASTER
|
||||||
#define CONFIG_SYS_DPAA_RMAN /* RMan */
|
#define CONFIG_SYS_DPAA_RMAN /* RMan */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_NO_FLASH
|
#ifdef CONFIG_SYS_NO_FLASH
|
||||||
|
|
|
@ -28,7 +28,6 @@
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#define CONFIG_DEEP_SLEEP
|
#define CONFIG_DEEP_SLEEP
|
||||||
|
@ -42,7 +41,6 @@
|
||||||
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
|
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xqds/t1024_pbi.cfg
|
||||||
#define CONFIG_SPL_FLUSH_IMAGE
|
#define CONFIG_SPL_FLUSH_IMAGE
|
||||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
||||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||||
#define CONFIG_SPL_PAD_TO 0x40000
|
#define CONFIG_SPL_PAD_TO 0x40000
|
||||||
|
|
|
@ -28,7 +28,6 @@
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
|
@ -45,7 +44,6 @@
|
||||||
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
|
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
|
||||||
#define CONFIG_SPL_FLUSH_IMAGE
|
#define CONFIG_SPL_FLUSH_IMAGE
|
||||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x30001000
|
#define CONFIG_SYS_TEXT_BASE 0x30001000
|
||||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||||
#define CONFIG_SPL_PAD_TO 0x40000
|
#define CONFIG_SPL_PAD_TO 0x40000
|
||||||
|
|
|
@ -69,8 +69,6 @@
|
||||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_NO_FLASH
|
#ifdef CONFIG_SYS_NO_FLASH
|
||||||
|
|
|
@ -24,7 +24,6 @@
|
||||||
|
|
||||||
#define CONFIG_SPL_FLUSH_IMAGE
|
#define CONFIG_SPL_FLUSH_IMAGE
|
||||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x30001000
|
#define CONFIG_SYS_TEXT_BASE 0x30001000
|
||||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||||
#define CONFIG_SPL_PAD_TO 0x40000
|
#define CONFIG_SPL_PAD_TO 0x40000
|
||||||
|
@ -180,8 +179,6 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
|
||||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#ifndef CONFIG_SYS_NO_FLASH
|
#ifndef CONFIG_SYS_NO_FLASH
|
||||||
|
|
|
@ -41,7 +41,6 @@
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#ifdef CONFIG_RAMBOOT_PBL
|
#ifdef CONFIG_RAMBOOT_PBL
|
||||||
|
@ -49,7 +48,6 @@
|
||||||
|
|
||||||
#define CONFIG_SPL_FLUSH_IMAGE
|
#define CONFIG_SPL_FLUSH_IMAGE
|
||||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
||||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||||
#define CONFIG_SPL_PAD_TO 0x40000
|
#define CONFIG_SPL_PAD_TO 0x40000
|
||||||
|
|
|
@ -34,7 +34,6 @@
|
||||||
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
|
||||||
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
#define CONFIG_FSL_IFC /* Enable IFC Support */
|
||||||
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#ifdef CONFIG_RAMBOOT_PBL
|
#ifdef CONFIG_RAMBOOT_PBL
|
||||||
|
@ -42,7 +41,6 @@
|
||||||
|
|
||||||
#define CONFIG_SPL_FLUSH_IMAGE
|
#define CONFIG_SPL_FLUSH_IMAGE
|
||||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
||||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||||
#define CONFIG_SPL_PAD_TO 0x40000
|
#define CONFIG_SPL_PAD_TO 0x40000
|
||||||
|
|
|
@ -24,7 +24,6 @@
|
||||||
#else
|
#else
|
||||||
#define CONFIG_SPL_FLUSH_IMAGE
|
#define CONFIG_SPL_FLUSH_IMAGE
|
||||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
||||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||||
#define CONFIG_SPL_PAD_TO 0x40000
|
#define CONFIG_SPL_PAD_TO 0x40000
|
||||||
|
|
|
@ -23,7 +23,6 @@
|
||||||
#else
|
#else
|
||||||
#define CONFIG_SPL_FLUSH_IMAGE
|
#define CONFIG_SPL_FLUSH_IMAGE
|
||||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
#define CONFIG_SYS_TEXT_BASE 0x00201000
|
||||||
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
|
||||||
#define CONFIG_SPL_PAD_TO 0x40000
|
#define CONFIG_SPL_PAD_TO 0x40000
|
||||||
|
@ -85,8 +84,6 @@
|
||||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -124,8 +124,6 @@
|
||||||
|
|
||||||
#define CONFIG_MP
|
#define CONFIG_MP
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW
|
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#define CONFIG_CMD_SATA
|
#define CONFIG_CMD_SATA
|
||||||
|
|
|
@ -42,7 +42,6 @@
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
#define CONFIG_ENABLE_36BIT_PHYS
|
#define CONFIG_ENABLE_36BIT_PHYS
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
|
|
||||||
#ifdef CONFIG_PHYS_64BIT
|
#ifdef CONFIG_PHYS_64BIT
|
||||||
#define CONFIG_ADDR_MAP
|
#define CONFIG_ADDR_MAP
|
||||||
|
|
|
@ -69,8 +69,6 @@
|
||||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_NO_FLASH
|
#ifdef CONFIG_SYS_NO_FLASH
|
||||||
|
|
|
@ -59,8 +59,6 @@
|
||||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
||||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
#define CONFIG_SYS_NO_FLASH
|
#define CONFIG_SYS_NO_FLASH
|
||||||
|
|
|
@ -46,8 +46,6 @@
|
||||||
|
|
||||||
#define CONFIG_SYS_DPAA_RMAN /* RMan */
|
#define CONFIG_SYS_DPAA_RMAN /* RMan */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
|
|
||||||
/* Environment in SPI Flash */
|
/* Environment in SPI Flash */
|
||||||
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
#define CONFIG_SYS_EXTRA_ENV_RELOC
|
||||||
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
#define CONFIG_ENV_IS_IN_SPI_FLASH
|
||||||
|
|
|
@ -174,7 +174,6 @@
|
||||||
#define CONFIG_SPL_MMC_MINIMAL
|
#define CONFIG_SPL_MMC_MINIMAL
|
||||||
#define CONFIG_SPL_FLUSH_IMAGE
|
#define CONFIG_SPL_FLUSH_IMAGE
|
||||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x11001000
|
#define CONFIG_SYS_TEXT_BASE 0x11001000
|
||||||
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
|
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
|
||||||
#define CONFIG_SPL_PAD_TO 0x20000
|
#define CONFIG_SPL_PAD_TO 0x20000
|
||||||
|
@ -195,7 +194,6 @@
|
||||||
#define CONFIG_SPL_SPI_FLASH_MINIMAL
|
#define CONFIG_SPL_SPI_FLASH_MINIMAL
|
||||||
#define CONFIG_SPL_FLUSH_IMAGE
|
#define CONFIG_SPL_FLUSH_IMAGE
|
||||||
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
#define CONFIG_SYS_TEXT_BASE 0x11001000
|
#define CONFIG_SYS_TEXT_BASE 0x11001000
|
||||||
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
|
#define CONFIG_SPL_TEXT_BASE 0xf8f81000
|
||||||
#define CONFIG_SPL_PAD_TO 0x20000
|
#define CONFIG_SPL_PAD_TO 0x20000
|
||||||
|
@ -274,7 +272,6 @@
|
||||||
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
||||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW
|
|
||||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
|
|
|
@ -52,7 +52,6 @@
|
||||||
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
|
||||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW
|
|
||||||
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
#define CONFIG_TSEC_ENET /* tsec ethernet support */
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
|
|
|
@ -69,8 +69,6 @@
|
||||||
|
|
||||||
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
|
#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
|
* Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4]
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -31,8 +31,6 @@
|
||||||
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
|
||||||
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
|
#define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Only possible on E500 Version 2 or newer cores.
|
* Only possible on E500 Version 2 or newer cores.
|
||||||
*/
|
*/
|
||||||
|
|
|
@ -40,8 +40,6 @@
|
||||||
#define CONFIG_SRIO1 /* SRIO port 1 */
|
#define CONFIG_SRIO1 /* SRIO port 1 */
|
||||||
#define CONFIG_SRIO2 /* SRIO port 2 */
|
#define CONFIG_SRIO2 /* SRIO port 2 */
|
||||||
|
|
||||||
#define CONFIG_FSL_LAW /* Use common FSL init code */
|
|
||||||
|
|
||||||
#define CONFIG_ENV_OVERWRITE
|
#define CONFIG_ENV_OVERWRITE
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -30,7 +30,6 @@
|
||||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
||||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
||||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* DDR config
|
* DDR config
|
||||||
|
|
|
@ -31,7 +31,6 @@
|
||||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
||||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||||
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
|
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
|
||||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
|
||||||
#define CONFIG_FSL_ELBC 1
|
#define CONFIG_FSL_ELBC 1
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
|
@ -32,7 +32,6 @@
|
||||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
||||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||||
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
|
#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
|
||||||
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
|
|
||||||
#define CONFIG_FSL_ELBC 1
|
#define CONFIG_FSL_ELBC 1
|
||||||
|
|
||||||
/*
|
/*
|
||||||
|
|
Loading…
Reference in New Issue
Block a user