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armv8: lx2160a: add MMU table entries for PCIe
The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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3fbe8f0f44
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@ -257,6 +257,20 @@ static struct mm_region final_map[] = {
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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},
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#endif
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#ifdef SYS_PCIE5_PHYS_ADDR
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{ SYS_PCIE5_PHYS_ADDR, SYS_PCIE5_PHYS_ADDR,
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SYS_PCIE5_PHYS_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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#endif
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#ifdef SYS_PCIE6_PHYS_ADDR
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{ SYS_PCIE6_PHYS_ADDR, SYS_PCIE6_PHYS_ADDR,
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SYS_PCIE6_PHYS_SIZE,
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PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN
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},
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#endif
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#endif
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{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
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{ CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
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CONFIG_SYS_FSL_WRIOP1_SIZE,
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CONFIG_SYS_FSL_WRIOP1_SIZE,
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@ -44,6 +44,8 @@
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#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
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#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
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#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
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#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
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#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000
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#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x800000000
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#define SYS_PCIE5_PHYS_SIZE 0x800000000
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#define SYS_PCIE6_PHYS_SIZE 0x800000000
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#endif
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#endif
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#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
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#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
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#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
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#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
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@ -167,7 +167,19 @@
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#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
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#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_IMMR + 0x2500000)
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#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
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#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_IMMR + 0x2600000)
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#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
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#define CONFIG_SYS_PCIE4_ADDR (CONFIG_SYS_IMMR + 0x2700000)
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#ifdef CONFIG_ARCH_LS1088A
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#ifdef CONFIG_ARCH_LX2160A
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#define SYS_PCIE5_ADDR (CONFIG_SYS_IMMR + 0x2800000)
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#define SYS_PCIE6_ADDR (CONFIG_SYS_IMMR + 0x2900000)
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#endif
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#ifdef CONFIG_ARCH_LX2160A
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#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x8000000000ULL
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#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x8800000000ULL
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#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x9000000000ULL
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#define CONFIG_SYS_PCIE4_PHYS_ADDR 0x9800000000ULL
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#define SYS_PCIE5_PHYS_ADDR 0xa000000000ULL
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#define SYS_PCIE6_PHYS_ADDR 0xa800000000ULL
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#elif CONFIG_ARCH_LS1088A
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#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
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#define CONFIG_SYS_PCIE1_PHYS_ADDR 0x2000000000ULL
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#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
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#define CONFIG_SYS_PCIE2_PHYS_ADDR 0x2800000000ULL
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#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
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#define CONFIG_SYS_PCIE3_PHYS_ADDR 0x3000000000ULL
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