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armv8: ls1028a: configure PMU's PCTBENR to enable WDT
The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by: Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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@ -1154,7 +1154,8 @@ int timer_init(void)
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#ifdef CONFIG_FSL_LSCH3
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#ifdef CONFIG_FSL_LSCH3
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u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
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u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
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#endif
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#endif
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
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defined(CONFIG_ARCH_LS1028A)
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u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
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u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
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u32 svr_dev_id;
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u32 svr_dev_id;
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#endif
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#endif
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@ -1173,7 +1174,8 @@ int timer_init(void)
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out_le32(cltbenr, 0xf);
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out_le32(cltbenr, 0xf);
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#endif
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#endif
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
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#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \
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defined(CONFIG_ARCH_LS1028A)
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/*
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/*
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* In certain Layerscape SoCs, the clock for each core's
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* In certain Layerscape SoCs, the clock for each core's
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* has an enable bit in the PMU Physical Core Time Base Enable
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* has an enable bit in the PMU Physical Core Time Base Enable
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