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riscv: ae350: dts: Fix #interrupt-cells for plic0 in 32-bit 

All the device nodes that refer to plic0 as their interrupt parent
have 2 cells encoded in their interrupts property, but plic0 only
provides 1 cell in #interrupt-cells which is incorrect.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
This commit is contained in:
Bin Meng 2021-06-04 13:51:12 +08:00 committed by Leo Yu-Chi Liang
parent f050dd2b26
commit 048aff6d26
1 changed files with 1 additions and 1 deletions
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2
arch/riscv/dts/ae350_32.dts
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@ -135,7 +135,7 @@
plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
#interrupt-cells = <1>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0xe4000000 0x2000000>;
riscv,ndev=<71>;