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mmc: dw_mmc: support the DDR mode
Support the DDR mode at dw-mmc controller Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Lukasz Majewski <l.majewski@samsung.com> Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
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@ -284,8 +284,8 @@ static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
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static void dwmci_set_ios(struct mmc *mmc)
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static void dwmci_set_ios(struct mmc *mmc)
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{
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{
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struct dwmci_host *host = mmc->priv;
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struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
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u32 ctype;
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u32 ctype, regs;
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debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
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debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
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@ -304,6 +304,14 @@ static void dwmci_set_ios(struct mmc *mmc)
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dwmci_writel(host, DWMCI_CTYPE, ctype);
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dwmci_writel(host, DWMCI_CTYPE, ctype);
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regs = dwmci_readl(host, DWMCI_UHS_REG);
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if (mmc->card_caps & MMC_MODE_DDR_52MHz)
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regs |= DWMCI_DDR_MODE;
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else
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regs &= DWMCI_DDR_MODE;
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dwmci_writel(host, DWMCI_UHS_REG, regs);
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if (host->clksel)
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if (host->clksel)
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host->clksel(host);
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host->clksel(host);
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}
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}
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@ -123,6 +123,9 @@
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#define DWMCI_BMOD_IDMAC_FB (1 << 1)
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#define DWMCI_BMOD_IDMAC_FB (1 << 1)
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#define DWMCI_BMOD_IDMAC_EN (1 << 7)
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#define DWMCI_BMOD_IDMAC_EN (1 << 7)
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/* UHS register */
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#define DWMCI_DDR_MODE (1 << 16)
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/* quirks */
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/* quirks */
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#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
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#define DWMCI_QUIRK_DISABLE_SMU (1 << 0)
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