mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 17:10:42 +09:00
Merge branch 'master' of git://git.denx.de/u-boot-marvell
This commit is contained in:
Tom Rini
commit
03cae7261e
@ -181,7 +181,7 @@ static void kw_sysrst_check(void)
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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char *rev;
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char *rev = "??";
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u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
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u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
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@ -192,7 +192,13 @@ int print_cpuinfo(void)
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switch (revid) {
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case 0:
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rev = "Z0";
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if (devid == 0x6281)
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rev = "Z0";
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else if (devid == 0x6282)
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rev = "A0";
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break;
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case 1:
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rev = "A1";
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break;
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case 2:
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rev = "A0";
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@ -201,7 +207,6 @@ int print_cpuinfo(void)
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rev = "A1";
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break;
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default:
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rev = "??";
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break;
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}
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@ -20,7 +20,7 @@ NAND_PAGE_SIZE 0x0800
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# Configure RGMII-0 interface pad voltage to 1.8V
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DATA 0xffd100e0 0x1b1b1b9b
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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# Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xffd01400 0x43000c30 # DDR Configuration register
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# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
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# bit23-14: 0x0,
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@ -87,7 +87,7 @@ DATA 0xffd0141c 0x00000c52 # DDR Mode
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# bit6-4: 0x4, CL=5
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# bit7: 0x0, TestMode=0 normal
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# bit8: 0x0, DLL reset=0 normal
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# bit11-9: 0x6, auto-precharge write recovery ????????????
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# bit11-9: 0x6, auto-precharge write recovery
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# bit12: 0x0, PD must be zero
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# bit31-13: 0x0, required
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@ -11,7 +11,7 @@
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#
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# Boot Media configurations
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BOOT_FROM nand # change from nand to uart if building UART image
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BOOT_FROM nand
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NAND_ECC_MODE default
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NAND_PAGE_SIZE 0x0800
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@ -21,12 +21,12 @@ NAND_PAGE_SIZE 0x0800
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# Configure RGMII-0 interface pad voltage to 1.8V
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DATA 0xffd100e0 0x1b1b1b9b
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#Dram initalization for SINGLE x16 CL=5 @ 400MHz
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# Dram initalization for SINGLE x16 CL=5 @ 400MHz
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DATA 0xffd01400 0x43000c30 # DDR Configuration register
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# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
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# bit23-14: 0x0,
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# bit24: 0x1, enable exit self refresh mode on DDR access
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# bit25: 0x1, required
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# bit24: 0x1, enable exit self refresh mode on DDR access
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# bit25: 0x1, required
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# bit29-26: 0x0,
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# bit31-30: 0x1,
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@ -64,10 +64,10 @@ DATA 0xffd01410 0x0000000c # DDR Address Control
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# bit3-2: 11, Cs0size (1Gb)
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# bit5-4: 00, Cs1width (x8)
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# bit7-6: 11, Cs1size (1Gb)
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# bit9-8: 00, Cs2width (nonexistent
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# bit11-10: 00, Cs2size (nonexistent
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# bit13-12: 00, Cs3width (nonexistent
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# bit15-14: 00, Cs3size (nonexistent
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# bit9-8: 00, Cs2width (nonexistent)
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# bit11-10: 00, Cs2size (nonexistent)
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# bit13-12: 00, Cs3width (nonexistent)
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# bit15-14: 00, Cs3size (nonexistent)
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# bit16: 0, Cs0AddrSel
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# bit17: 0, Cs1AddrSel
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# bit18: 0, Cs2AddrSel
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@ -88,7 +88,7 @@ DATA 0xffd0141c 0x00000c52 # DDR Mode
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# bit6-4: 0x4, CL=5
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# bit7: 0x0, TestMode=0 normal
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# bit8: 0x0, DLL reset=0 normal
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# bit11-9: 0x6, auto-precharge write recovery ????????????
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# bit11-9: 0x6, auto-precharge write recovery
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# bit12: 0x0, PD must be zero
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# bit31-13: 0x0, required
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@ -148,8 +148,8 @@ DATA 0xffd0149c 0x0000e803 # CPU ODT Control
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DATA 0xffd01480 0x00000001 # DDR Initialization Control
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# bit0: 0x1, enable DDR init upon this register write
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DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
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DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
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DATA 0xffd20134 0x66666666 # L2 RAM Timing 0 Register
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DATA 0xffd20138 0x66666666 # L2 RAM Timing 1 Register
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# End of Header extension
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DATA 0x0 0x0
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@ -35,6 +35,10 @@
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_MVGBE_PORTS
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# define CONFIG_MVGBE_PORTS {0, 0}
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#endif
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#define MV_PHY_ADR_REQUEST 0xee
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#define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
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@ -12,6 +12,8 @@
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#ifndef _CONFIG_DOCKSTAR_H
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#define _CONFIG_DOCKSTAR_H
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#define CONFIG_SYS_GENERIC_BOARD
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/*
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* Version number information
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*/
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@ -15,6 +15,8 @@
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#ifndef _CONFIG_GOFLEXHOME_H
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#define _CONFIG_GOFLEXHOME_H
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#define CONFIG_SYS_GENERIC_BOARD
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/*
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* Version number information
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*/
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@ -1,5 +1,6 @@
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/*
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* (C) Copyright 2009
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* (C) Copyright 2009-2014
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* Gerald Kerma <dreagle@doukki.net>
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* Marvell Semiconductor <www.marvell.com>
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* Written-by: Siddarth Gore <gores@marvell.com>
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*
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@ -9,6 +10,8 @@
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#ifndef _CONFIG_GURUPLUG_H
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#define _CONFIG_GURUPLUG_H
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#define CONFIG_SYS_GENERIC_BOARD
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/*
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* Version number information
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*/
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@ -22,18 +25,37 @@
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#define CONFIG_MACH_GURUPLUG /* Machine type */
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#define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
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/*
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* Compression configuration
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*/
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#define CONFIG_BZIP2
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#define CONFIG_LZMA
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#define CONFIG_LZO
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/*
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* Enable device tree support
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*/
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#define CONFIG_OF_LIBFDT
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
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/*
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* Commands configuration
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*/
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#define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
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#include <config_cmd_default.h>
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#define CONFIG_CMD_BOOTZ
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#define CONFIG_CMD_DHCP
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#define CONFIG_CMD_ENV
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_MII
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#define CONFIG_CMD_NAND
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#define CONFIG_CMD_PING
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#define CONFIG_CMD_USB
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#define CONFIG_CMD_IDE
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#define CONFIG_CMD_FAT
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/*
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* mv-common.h should be defined after CMD configs since it used them
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@ -55,24 +77,38 @@
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* it has to be rounded to sector size
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*/
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#define CONFIG_ENV_SIZE 0x20000 /* 128k */
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#define CONFIG_ENV_ADDR 0x60000
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#define CONFIG_ENV_OFFSET 0x60000 /* env starts here */
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#define CONFIG_ENV_OFFSET 0xE0000 /* env starts here */
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/*
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* Default environment variables
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*/
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#define CONFIG_BOOTCOMMAND "setenv ethact egiga0; " \
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"${x_bootcmd_ethernet}; setenv ethact egiga1; " \
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"${x_bootcmd_ethernet}; ${x_bootcmd_usb}; ${x_bootcmd_kernel}; "\
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"setenv bootargs ${x_bootargs} ${x_bootargs_root}; " \
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"bootm 0x6400000;"
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#define CONFIG_BOOTCOMMAND \
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"setenv bootargs ${console} ${mtdparts} ${bootargs_root}; " \
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"ubi part root; " \
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"ubifsmount ubi:rootfs; " \
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"ubifsload 0x800000 ${kernel}; " \
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"ubifsload 0x700000 ${fdt}; " \
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"ubifsumount; " \
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"fdt addr 0x700000; fdt resize; fdt chosen; " \
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"bootz 0x800000 - 0x700000"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"x_bootcmd_ethernet=ping 192.168.2.1\0" \
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"x_bootcmd_usb=usb start\0" \
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"x_bootcmd_kernel=nand read.e 0x6400000 0x100000 0x400000\0" \
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"x_bootargs=console=ttyS0,115200\0" \
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"x_bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs\0"
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#define CONFIG_MTDPARTS \
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"mtdparts=orion_nand:" \
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"896K(uboot),128K(uboot_env)," \
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"-@1M(root)\0"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"console=console=ttyS0,115200\0" \
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"mtdids=nand0=orion_nand\0" \
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"mtdparts="CONFIG_MTDPARTS \
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"kernel=/boot/zImage\0" \
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"fdt=/boot/guruplug-server-plus.dtb\0" \
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"bootargs_root=ubi.mtd=2 root=ubi0:rootfs rootfstype=ubifs rw\0"
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#define MTDIDS_DEFAULT "nand0=orion_nand"
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#define MTDPARTS_DEFAULT \
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"mtdparts="CONFIG_MTDPARTS
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/*
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* Ethernet Driver configuration
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@ -89,6 +125,20 @@
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#define CONFIG_SYS_ATA_IDE0_OFFSET MV_SATA_PORT0_OFFSET
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#endif /*CONFIG_MVSATA_IDE*/
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/*
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* File system
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*/
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#define CONFIG_CMD_EXT2
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#define CONFIG_CMD_EXT4
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#define CONFIG_CMD_FAT
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#define CONFIG_CMD_JFFS2
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#define CONFIG_CMD_UBI
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#define CONFIG_CMD_UBIFS
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#define CONFIG_RBTREE
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#define CONFIG_MTD_DEVICE
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#define CONFIG_MTD_PARTITIONS
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#define CONFIG_CMD_MTDPARTS
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#define CONFIG_SYS_ALT_MEMTEST
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#endif /* _CONFIG_GURUPLUG_H */
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@ -9,6 +9,8 @@
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#ifndef _CONFIG_IB62x0_H
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#define _CONFIG_IB62x0_H
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#define CONFIG_SYS_GENERIC_BOARD
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/*
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* Version number information
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*/
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@ -9,6 +9,8 @@
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#ifndef _CONFIG_ICONNECT_H
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#define _CONFIG_ICONNECT_H
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#define CONFIG_SYS_GENERIC_BOARD
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/*
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* Version number information
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*/
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@ -13,6 +13,8 @@
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#ifndef _CONFIG_POGO_E02_H
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#define _CONFIG_POGO_E02_H
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#define CONFIG_SYS_GENERIC_BOARD
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/*
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* Machine type definition and ID
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*/
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@ -10,6 +10,8 @@
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#ifndef _CONFIG_SHEEVAPLUG_H
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#define _CONFIG_SHEEVAPLUG_H
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#define CONFIG_SYS_GENERIC_BOARD
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/*
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* Version number information
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*/
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