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mips: bmips: add bcm6345-rst driver support for BCM63268

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This driver can control up to 32 clocks.

Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Álvaro Fernández Rojas 2017-05-03 15:10:24 +02:00 committed by Daniel Schwierzeck
parent 78118211fb
commit 02bb1fa09e
2 changed files with 39 additions and 0 deletions
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7
arch/mips/dts/brcm,bcm63268.dtsi
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@ -6,6 +6,7 @@
#include <dt-bindings/clock/bcm63268-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/reset/bcm63268-reset.h>
#include "skeleton.dtsi"
/ {
@ -76,6 +77,12 @@
mask = <0x1>;
};
periph_rst: reset-controller@10000010 {
compatible = "brcm,bcm6345-reset";
reg = <0x10000010 0x4>;
#reset-cells = <1>;
};
gpio1: gpio-controller@100000c0 {
compatible = "brcm,bcm6345-gpio";
reg = <0x100000c0 0x4>, <0x100000c8 0x4>;

32
include/dt-bindings/reset/bcm63268-reset.h Normal file
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@ -0,0 +1,32 @@
/*
* Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
*
* Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef __DT_BINDINGS_RESET_BCM63268_H
#define __DT_BINDINGS_RESET_BCM63268_H
#define BCM63268_RST_SPI 0
#define BCM63268_RST_IPSEC 1
#define BCM63268_RST_EPHY 2
#define BCM63268_RST_SAR 3
#define BCM63268_RST_ENETSW 4
#define BCM63268_RST_USBS 5
#define BCM63268_RST_USBH 6
#define BCM63268_RST_PCM 7
#define BCM63268_RST_PCIE_CORE 8
#define BCM63268_RST_PCIE 9
#define BCM63268_RST_PCIE_EXT 10
#define BCM63268_RST_WLAN_SHIM 11
#define BCM63268_RST_DDR_PHY 12
#define BCM63268_RST_FAP0 13
#define BCM63268_RST_WLAN_UBUS 14
#define BCM63268_RST_DECT 15
#define BCM63268_RST_FAP1 16
#define BCM63268_RST_PCIE_HARD 17
#define BCM63268_RST_GPHY 18
#endif /* __DT_BINDINGS_RESET_BCM63268_H */