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ppc4xx: Update Sequoia/Rainier bootstrap command

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As suggested by David Mitchell, here an update for the Sequoia/Rainier
bootstrap command.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2007-08-16 09:52:29 +02:00
parent f31b0aecb5
commit 02ba7022f6
1 changed files with 159 additions and 50 deletions
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209
board/amcc/sequoia/cmd_sequoia.c
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@ -26,76 +26,185 @@
#include <command.h> #include <command.h>
#include <i2c.h> #include <i2c.h>
static u8 boot_533_nor[] = { /*
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, * There are 2 versions of production Sequoia & Rainier platforms.
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 * The primary difference is the reference clock. Those with
* 33333333 reference clocks will also have 667MHz rated
* processors. Not enough differences to have unique clock
* settings.
*
* NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
* values are independent of the rest of the clock settings.
*
* All Sequoias & Rainiers select from two possible EEPROMs in Boot
* Config F. One for 33MHz PCI, one for 66MHz PCI. The following
* values are for the 33MHz PCI configuration. Byte 5 (0 base) is
* the only value affected for a 66MHz PCI and simply needs a +0x10.
*/
#define NAND_COMPATIBLE 0x01
#define NOR_COMPATIBLE 0x02
/* check with Stefan on CFG_I2C_EEPROM_ADDR */
#define I2C_EEPROM_ADDR 0x52
static char *config_labels[] = {
"CPU: 333 PLB: 133 OPB: 66 EBC: 66",
"CPU: 333 PLB: 166 OPB: 83 EBC: 55",
"CPU: 400 PLB: 133 OPB: 66 EBC: 66",
"CPU: 400 PLB: 160 OPB: 80 EBC: 53",
"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
NULL
}; };
static u8 boot_533_nand[] = { static u8 boot_configs[][17] = {
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10, {
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00 (NOR_COMPATIBLE),
0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
(NAND_COMPATIBLE | NOR_COMPATIBLE),
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
},
{
0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
}
}; };
static u8 boot_667_nor[] = { /*
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, * Bytes 6,8,9,11 change for NAND boot
0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00 */
}; static u8 nand_boot[] = {
0xd0, 0xa0, 0x68, 0x58
static u8 boot_667_nand[] = {
0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10,
0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
}; };
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{ {
u8 chip; u8 *buf, bNAND;
u8 *buf; int x, y, nbytes, selcfg;
int cpu_freq; extern char console_buffer[];
if (argc < 3) { if (argc < 2) {
printf("Usage:\n%s\n", cmdtp->usage); printf("Usage:\n%s\n", cmdtp->usage);
return 1; return 1;
} }
cpu_freq = simple_strtol(argv[1], NULL, 10); if ((strcmp(argv[1], "nor") != 0) &&
if (!((cpu_freq == 533) || (cpu_freq == 667))) { (strcmp(argv[1], "nand") != 0)) {
printf("Unsupported cpu-frequency - only 533 and 667 supported\n");
return 1;
}
/* use 0x52 as I2C EEPROM address for now */
chip = 0x52;
if ((strcmp(argv[2], "nor") != 0) &&
(strcmp(argv[2], "nand") != 0)) {
printf("Unsupported boot-device - only nor|nand support\n"); printf("Unsupported boot-device - only nor|nand support\n");
return 1; return 1;
} }
if (strcmp(argv[2], "nand") == 0) { /* set the nand flag based on provided input */
switch (cpu_freq) { if ((strcmp(argv[1], "nand") == 0))
default: bNAND = 1;
case 533: else
buf = boot_533_nand; bNAND = 0;
break;
case 667: printf("Available configurations: \n\n");
buf = boot_667_nand;
break; if (bNAND) {
for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
/* filter on nand compatible */
if (boot_configs[x][0] & NAND_COMPATIBLE) {
printf(" %d - %s\n", (y+1), config_labels[x]);
y++;
}
} }
} else { } else {
switch (cpu_freq) { for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
default: /* filter on nor compatible */
case 533: if (boot_configs[x][0] & NOR_COMPATIBLE) {
buf = boot_533_nor; printf(" %d - %s\n", (y+1), config_labels[x]);
break; y++;
case 667: }
buf = boot_667_nor;
break;
} }
} }
if (i2c_write(chip, 0, 1, buf, 16) != 0) do {
printf("Error writing to EEPROM at address 0x%x\n", chip); nbytes = readline(" Selection [1-x / quit]: ");
if (nbytes) {
if (strcmp(console_buffer, "quit") == 0)
return 0;
selcfg = simple_strtol(console_buffer, NULL, 10);
if ((selcfg < 1) || (selcfg > y))
nbytes = 0;
}
} while (nbytes == 0);
y = (selcfg - 1);
for (x = 0; boot_configs[x][0] != 0; x++) {
if (bNAND) {
if (boot_configs[x][0] & NAND_COMPATIBLE) {
if (y > 0)
y--;
else if (y < 1)
break;
}
} else {
if (boot_configs[x][0] & NOR_COMPATIBLE) {
if (y > 0)
y--;
else if (y < 1)
break;
}
}
}
buf = &boot_configs[x][1];
if (bNAND) {
buf[6] = nand_boot[0];
buf[8] = nand_boot[1];
buf[9] = nand_boot[2];
buf[11] = nand_boot[3];
}
/* check CPLD register +5 for PCI 66MHz flag */
if (in8(CFG_BCSR_BASE + 5) & 0x01)
buf[5] += 0x10;
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000); udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
printf("Done\n"); printf("Done\n");
@ -105,7 +214,7 @@ static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
} }
U_BOOT_CMD( U_BOOT_CMD(
bootstrap, 3, 0, do_bootstrap, bootstrap, 2, 0, do_bootstrap,
"bootstrap - program the I2C bootstrap EEPROM\n", "bootstrap - program the I2C bootstrap EEPROM\n",
"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n" "<nand|nor> - strap to boot from NAND or NOR flash\n"
); );