From e81c0aba9a5e56d6e9b25a669c582827f999302f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Thu, 13 Oct 2011 14:55:59 -0500 Subject: [PATCH 01/10] fm-eth: Don't mark the MAC we use for MDIO as disabled in device tree FM1-DTSEC1's MAC was being marked as disabled if the port was not configured based on the SoC configuration. However we utilize the MAC interface for MDIO and thus should NOT mark it disabled. Signed-off-by: Kumar Gala --- drivers/net/fm/init.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index 512d7dd3de..953c359e6e 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -183,6 +183,8 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) { int off, ph; phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset; + u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS + + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET; off = fdt_node_offset_by_compat_reg(blob, prop, paddr); @@ -195,9 +197,13 @@ static void ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) /* board code might have caused offset to change */ off = fdt_node_offset_by_compat_reg(blob, prop, paddr); - /* disable both the mac node and the node that has a handle to it */ - fdt_setprop_string(blob, off, "status", "disabled"); + /* Don't disable FM1-DTSEC1 MAC as its used for MDIO */ + if (paddr != dtsec1_addr) { + /* disable the mac node */ + fdt_setprop_string(blob, off, "status", "disabled"); + } + /* disable the node point to the mac */ ph = fdt_get_phandle(blob, off); do_fixup_by_prop(blob, "fsl,fman-mac", &ph, sizeof(ph), "status", "disabled", strlen("disabled") + 1, 1); From f5b9e736418422f9f3501b9854294b38275f4abd Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 14 Oct 2011 03:17:56 -0500 Subject: [PATCH 02/10] fm: Don't allow disabling of FM1-DTSEC1 The MDIO controller to talk to external PHYs is on FM1-DTSEC1 so don't allow disabling. If we disable it we end up powering the block down in the SoC and thus can't communicate to any external PHYs. Signed-off-by: Kumar Gala --- drivers/net/fm/p1023.c | 5 +++++ drivers/net/fm/p3060.c | 5 +++++ drivers/net/fm/p4080.c | 5 +++++ drivers/net/fm/p5020.c | 5 +++++ 4 files changed, 20 insertions(+) diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c index b17dc40b8a..9765da5b23 100644 --- a/drivers/net/fm/p1023.c +++ b/drivers/net/fm/p1023.c @@ -39,6 +39,11 @@ static int is_device_disabled(enum fm_port port) void fman_disable_port(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* don't allow disabling of DTSEC1 as its needed for MDIO */ + if (port == FM1_DTSEC1) + return; + setbits_be32(&gur->devdisr, port_to_devdisr[port]); } diff --git a/drivers/net/fm/p3060.c b/drivers/net/fm/p3060.c index 176e1d292c..c9748a954c 100644 --- a/drivers/net/fm/p3060.c +++ b/drivers/net/fm/p3060.c @@ -45,6 +45,11 @@ static int is_device_disabled(enum fm_port port) void fman_disable_port(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* don't allow disabling of DTSEC1 as its needed for MDIO */ + if (port == FM1_DTSEC1) + return; + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); } diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c index 791caab7ec..9dc6049c36 100644 --- a/drivers/net/fm/p4080.c +++ b/drivers/net/fm/p4080.c @@ -47,6 +47,11 @@ static int is_device_disabled(enum fm_port port) void fman_disable_port(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* don't allow disabling of DTSEC1 as its needed for MDIO */ + if (port == FM1_DTSEC1) + return; + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); } diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c index 69c27d2237..a7a6e43fe2 100644 --- a/drivers/net/fm/p5020.c +++ b/drivers/net/fm/p5020.c @@ -43,6 +43,11 @@ static int is_device_disabled(enum fm_port port) void fman_disable_port(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + + /* don't allow disabling of DTSEC1 as its needed for MDIO */ + if (port == FM1_DTSEC1) + return; + setbits_be32(&gur->devdisr2, port_to_devdisr[port]); } From 1a0c64219df1fe4f8c40ed2ecaa0da1b4e0e26f7 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 14 Oct 2011 00:01:23 -0500 Subject: [PATCH 03/10] powerpc/85xx: Update setting of SRIO LIODNs Properly set the LIODN values associated with SRIO controller. On P4080/P3060 we have an LIODN per port and one for the RMU. On P2041/P3041/P5020 we have 2 LIODNs per port. Update the tables for all of these devices to properly handle both styles. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/liodn.c | 18 ++++++++++++++++++ arch/powerpc/cpu/mpc85xx/p2041_ids.c | 6 ++++++ arch/powerpc/cpu/mpc85xx/p3041_ids.c | 6 ++++++ arch/powerpc/cpu/mpc85xx/p3060_ids.c | 10 +++++++--- arch/powerpc/cpu/mpc85xx/p4080_ids.c | 10 +++++++--- arch/powerpc/cpu/mpc85xx/p5020_ids.c | 6 ++++++ arch/powerpc/include/asm/fsl_liodn.h | 22 ++++++++++++++++++++++ 7 files changed, 72 insertions(+), 6 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index e0ea502a05..e14de9dc96 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -40,6 +40,21 @@ int get_dpaa_liodn(enum fsl_dpaa_dev dpaa_dev, u32 *liodns, int liodn_offset) return liodn_bases[dpaa_dev].num_ids; } +static void set_srio_liodn(struct srio_liodn_id_table *tbl, int size) +{ + int i; + + for (i = 0; i < size; i++) { + unsigned long reg_off = tbl[i].reg_offset[0]; + out_be32((u32 *)reg_off, tbl[i].id[0]); + + if (tbl[i].num_ids == 2) { + reg_off = tbl[i].reg_offset[1]; + out_be32((u32 *)reg_off, tbl[i].id[1]); + } + } +} + static void set_liodn(struct liodn_id_table *tbl, int size) { int i; @@ -138,6 +153,9 @@ void set_liodns(void) /* setup general liodn offsets */ set_liodn(liodn_tbl, liodn_tbl_sz); + /* setup SRIO port liodns */ + set_srio_liodn(srio_liodn_tbl, srio_liodn_tbl_sz); + /* setup SEC block liodn bases & offsets if we have one */ if (IS_E_PROCESSOR(get_svr())) { set_liodn(sec_liodn_tbl, sec_liodn_tbl_sz); diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 8d254961e2..8d7c354f95 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -40,6 +40,12 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_2(1, 199, 200), + SET_SRIO_LIODN_2(2, 201, 202), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(31), diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 96f32725f5..7ce9fc4cc5 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -40,6 +40,12 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_2(1, 199, 200), + SET_SRIO_LIODN_2(2, 201, 202), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(31), diff --git a/arch/powerpc/cpu/mpc85xx/p3060_ids.c b/arch/powerpc/cpu/mpc85xx/p3060_ids.c index 07703d44eb..d32142f636 100644 --- a/arch/powerpc/cpu/mpc85xx/p3060_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3060_ids.c @@ -40,6 +40,12 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_1(1, 198), + SET_SRIO_LIODN_1(2, 199), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + struct liodn_id_table liodn_tbl[] = { SET_USB_LIODN(1, "fsl-usb2-mph", 127), SET_USB_LIODN(2, "fsl-usb2-dr", 157), @@ -50,9 +56,7 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, 196), SET_DMA_LIODN(2, 197), - SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0), + SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000), #ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(31), diff --git a/arch/powerpc/cpu/mpc85xx/p4080_ids.c b/arch/powerpc/cpu/mpc85xx/p4080_ids.c index 560c02ad57..a6ea6af64f 100644 --- a/arch/powerpc/cpu/mpc85xx/p4080_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p4080_ids.c @@ -40,6 +40,12 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_1(1, 198), + SET_SRIO_LIODN_1(2, 199), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + struct liodn_id_table liodn_tbl[] = { SET_USB_LIODN(1, "fsl-usb2-mph", 127), SET_USB_LIODN(2, "fsl-usb2-dr", 157), @@ -53,9 +59,7 @@ struct liodn_id_table liodn_tbl[] = { SET_DMA_LIODN(1, 196), SET_DMA_LIODN(2, 197), - SET_GUTS_LIODN("fsl,rapidio-delta", 198, rio1liodnr, 0), - SET_GUTS_LIODN(NULL, 199, rio2liodnr, 0), - SET_GUTS_LIODN(NULL, 200, rmuliodnr, 0), + SET_GUTS_LIODN("fsl,srio-rmu", 200, rmuliodnr, 0xd3000), #ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(31), diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index 4254dd56c7..65d8775551 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -40,6 +40,12 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = { }; #endif +struct srio_liodn_id_table srio_liodn_tbl[] = { + SET_SRIO_LIODN_2(1, 199, 200), + SET_SRIO_LIODN_2(2, 201, 202), +}; +int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl); + struct liodn_id_table liodn_tbl[] = { #ifdef CONFIG_SYS_DPAA_QBMAN SET_QMAN_LIODN(31), diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 9ad104eb8a..c65f76370f 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -25,6 +25,26 @@ #include +struct srio_liodn_id_table { + u32 id[2]; + unsigned long reg_offset[2]; + u8 num_ids; + u8 portid; +}; +#define SET_SRIO_LIODN_1(port, idA) \ + { .id = { idA }, .num_ids = 1, .portid = port, \ + .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ + + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + } + +#define SET_SRIO_LIODN_2(port, idA, idB) \ + { .id = { idA, idB }, .num_ids = 2, .portid = port, \ + .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ + + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \ + + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + } + struct liodn_id_table { const char * compat; u32 id[2]; @@ -158,7 +178,9 @@ extern void fdt_fixup_liodn(void *blob); extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; extern struct liodn_id_table raide_liodn_tbl[]; extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; +extern struct srio_liodn_id_table srio_liodn_tbl[]; extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz; extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz; +extern int srio_liodn_tbl_sz; #endif From 9c42ef61454ff7b4da23767366620a947b2486b5 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 14 Oct 2011 00:03:58 -0500 Subject: [PATCH 04/10] powerpc/85xx: Update device tree handling for SRIO Update device tree handling for SRIO controller to support updated fsl,srio device tree binding. We handle disabling of individual ports, the whole controller, RMU, and RMAN. Additionally, we setup the SRIO related LIODNs in the device tree. Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/liodn.c | 31 ++++++++++++++ arch/powerpc/cpu/mpc8xxx/fdt.c | 72 +++++++++++++++++++++++++++----- 2 files changed, 93 insertions(+), 10 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index e14de9dc96..8df9f8e850 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -184,6 +184,35 @@ void set_liodns(void) #endif } +static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl) +{ + int i, srio_off; + + /* search for srio node, if doesn't exist just return - nothing todo */ + srio_off = fdt_node_offset_by_compatible(blob, -1, "fsl,srio"); + if (srio_off < 0) + return ; + + for (i = 0; i < srio_liodn_tbl_sz; i++) { + int off, portid = tbl[i].portid; + + off = fdt_node_offset_by_prop_value(blob, srio_off, + "cell-index", &portid, 4); + if (off >= 0) { + off = fdt_setprop(blob, off, "fsl,liodn", + &tbl[i].id[0], + sizeof(u32) * tbl[i].num_ids); + if (off > 0) + printf("WARNING unable to set fsl,liodn for " + "fsl,srio port %d: %s\n", + portid, fdt_strerror(off)); + } else { + debug("WARNING: couldn't set fsl,liodn for srio: %s.\n", + fdt_strerror(off)); + } + } +} + static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) { int i; @@ -213,6 +242,8 @@ static void fdt_fixup_liodn_tbl(void *blob, struct liodn_id_table *tbl, int sz) void fdt_fixup_liodn(void *blob) { + fdt_fixup_srio_liodn(blob, srio_liodn_tbl); + fdt_fixup_liodn_tbl(blob, liodn_tbl, liodn_tbl_sz); #ifdef CONFIG_SYS_DPAA_FMAN fdt_fixup_liodn_tbl(blob, fman1_liodn_tbl, fman1_liodn_tbl_sz); diff --git a/arch/powerpc/cpu/mpc8xxx/fdt.c b/arch/powerpc/cpu/mpc8xxx/fdt.c index 5bb9f53542..112c603532 100644 --- a/arch/powerpc/cpu/mpc8xxx/fdt.c +++ b/arch/powerpc/cpu/mpc8xxx/fdt.c @@ -275,21 +275,73 @@ int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc) } #ifdef CONFIG_SYS_SRIO +static inline void ft_disable_srio_port(void *blob, int srio_off, int port) +{ + int off = fdt_node_offset_by_prop_value(blob, srio_off, + "cell-index", &port, 4); + if (off >= 0) { + off = fdt_setprop_string(blob, off, "status", "disabled"); + if (off > 0) + printf("WARNING unable to set status for fsl,srio " + "port %d: %s\n", port, fdt_strerror(off)); + } +} + +static inline void ft_disable_rman(void *blob) +{ + int off = fdt_node_offset_by_compatible(blob, -1, "fsl,rman"); + if (off >= 0) { + off = fdt_setprop_string(blob, off, "status", "disabled"); + if (off > 0) + printf("WARNING unable to set status for fsl,rman %s\n", + fdt_strerror(off)); + } +} + +static inline void ft_disable_rmu(void *blob) +{ + int off = fdt_node_offset_by_compatible(blob, -1, "fsl,srio-rmu"); + if (off >= 0) { + off = fdt_setprop_string(blob, off, "status", "disabled"); + if (off > 0) + printf("WARNING unable to set status for " + "fsl,srio-rmu %s\n", fdt_strerror(off)); + } +} + void ft_srio_setup(void *blob) { + int srio1_used = 0, srio2_used = 0; + int srio_off; + + /* search for srio node, if doesn't exist just return - nothing todo */ + srio_off = fdt_node_offset_by_compatible(blob, -1, "fsl,srio"); + if (srio_off < 0) + return ; + #ifdef CONFIG_SRIO1 - if (!is_serdes_configured(SRIO1)) { - fdt_del_node_and_alias(blob, "rio0"); - } -#else - fdt_del_node_and_alias(blob, "rio0"); + if (is_serdes_configured(SRIO1)) + srio1_used = 1; #endif #ifdef CONFIG_SRIO2 - if (!is_serdes_configured(SRIO2)) { - fdt_del_node_and_alias(blob, "rio1"); - } -#else - fdt_del_node_and_alias(blob, "rio1"); + if (is_serdes_configured(SRIO2)) + srio2_used = 1; #endif + + /* mark port1 disabled */ + if (!srio1_used) + ft_disable_srio_port(blob, srio_off, 1); + + /* mark port2 disabled */ + if (!srio2_used) + ft_disable_srio_port(blob, srio_off, 2); + + /* if both ports not used, disable controller, rmu and rman */ + if (!srio1_used && !srio2_used) { + fdt_setprop_string(blob, srio_off, "status", "disabled"); + + ft_disable_rman(blob); + ft_disable_rmu(blob); + } } #endif From 4d28db8a1e8b90e1e3ffd95d7f949b849e33fa2f Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Fri, 14 Oct 2011 13:28:52 -0500 Subject: [PATCH 05/10] powerpc/85xx: Add support for RMan LIODN initialization This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/liodn.c | 39 ++++++++++++++++++++++++++ arch/powerpc/cpu/mpc85xx/p2041_ids.c | 14 +++++++++ arch/powerpc/cpu/mpc85xx/p3041_ids.c | 14 +++++++++ arch/powerpc/cpu/mpc85xx/p5020_ids.c | 14 +++++++++ arch/powerpc/cpu/mpc85xx/portals.c | 6 ++++ arch/powerpc/include/asm/fsl_liodn.h | 8 ++++++ arch/powerpc/include/asm/fsl_portals.h | 4 +++ arch/powerpc/include/asm/immap_85xx.h | 13 +++++++++ include/configs/P2041RDB.h | 1 + include/configs/P3041DS.h | 1 + include/configs/P5020DS.h | 1 + 11 files changed, 115 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index 8df9f8e850..11881c9489 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -148,6 +148,34 @@ static void setup_raide_liodn_base(void) } #endif +#ifdef CONFIG_SYS_DPAA_RMAN +static void set_rman_liodn(struct liodn_id_table *tbl, int size) +{ + int i; + struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR; + + for (i = 0; i < size; i++) { + /* write the RMan block number */ + out_be32(&rman->mmitar, i); + /* write the liodn offset corresponding to the block */ + out_be32((u32 *)(tbl[i].reg_offset), tbl[i].id[0]); + } +} + +static void setup_rman_liodn_base(struct liodn_id_table *tbl, int size) +{ + int i; + struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR; + u32 base = liodn_bases[FSL_HW_PORTAL_RMAN].id[0]; + + out_be32(&rman->mmliodnbr, base); + + /* update liodn offset */ + for (i = 0; i < size; i++) + tbl[i].id[0] += base; +} +#endif + void set_liodns(void) { /* setup general liodn offsets */ @@ -182,6 +210,13 @@ void set_liodns(void) set_liodn(raide_liodn_tbl, raide_liodn_tbl_sz); setup_raide_liodn_base(); #endif + +#ifdef CONFIG_SYS_DPAA_RMAN + /* setup RMan liodn offsets */ + set_rman_liodn(rman_liodn_tbl, rman_liodn_tbl_sz); + /* setup RMan liodn base */ + setup_rman_liodn_base(rman_liodn_tbl, rman_liodn_tbl_sz); +#endif } static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl) @@ -256,4 +291,8 @@ void fdt_fixup_liodn(void *blob) #ifdef CONFIG_SYS_FSL_RAID_ENGINE fdt_fixup_liodn_tbl(blob, raide_liodn_tbl, raide_liodn_tbl_sz); #endif + +#ifdef CONFIG_SYS_DPAA_RMAN + fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz); +#endif } diff --git a/arch/powerpc/cpu/mpc85xx/p2041_ids.c b/arch/powerpc/cpu/mpc85xx/p2041_ids.c index 8d7c354f95..b99b54d6bc 100644 --- a/arch/powerpc/cpu/mpc85xx/p2041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p2041_ids.c @@ -104,6 +104,17 @@ struct liodn_id_table sec_liodn_tbl[] = { }; int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), #ifdef CONFIG_SYS_DPAA_FMAN @@ -112,4 +123,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_PME [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), #endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80), +#endif }; diff --git a/arch/powerpc/cpu/mpc85xx/p3041_ids.c b/arch/powerpc/cpu/mpc85xx/p3041_ids.c index 7ce9fc4cc5..c50b442801 100644 --- a/arch/powerpc/cpu/mpc85xx/p3041_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p3041_ids.c @@ -103,6 +103,17 @@ struct liodn_id_table sec_liodn_tbl[] = { }; int sec_liodn_tbl_sz = ARRAY_SIZE(sec_liodn_tbl); +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), #ifdef CONFIG_SYS_DPAA_FMAN @@ -111,4 +122,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_DPAA_PME [FSL_HW_PORTAL_PME] = SET_LIODN_BASE_2(136, 172), #endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80), +#endif }; diff --git a/arch/powerpc/cpu/mpc85xx/p5020_ids.c b/arch/powerpc/cpu/mpc85xx/p5020_ids.c index 65d8775551..ff57a193bb 100644 --- a/arch/powerpc/cpu/mpc85xx/p5020_ids.c +++ b/arch/powerpc/cpu/mpc85xx/p5020_ids.c @@ -113,6 +113,17 @@ struct liodn_id_table raide_liodn_tbl[] = { int raide_liodn_tbl_sz = ARRAY_SIZE(raide_liodn_tbl); #endif +#ifdef CONFIG_SYS_DPAA_RMAN +struct liodn_id_table rman_liodn_tbl[] = { + /* Set RMan block 0-3 liodn offset */ + SET_RMAN_LIODN(0, 6), + SET_RMAN_LIODN(1, 7), + SET_RMAN_LIODN(2, 8), + SET_RMAN_LIODN(3, 9), +}; +int rman_liodn_tbl_sz = ARRAY_SIZE(rman_liodn_tbl); +#endif + struct liodn_id_table liodn_bases[] = { [FSL_HW_PORTAL_SEC] = SET_LIODN_BASE_2(64, 100), #ifdef CONFIG_SYS_DPAA_FMAN @@ -124,4 +135,7 @@ struct liodn_id_table liodn_bases[] = { #ifdef CONFIG_SYS_FSL_RAID_ENGINE [FSL_HW_PORTAL_RAID_ENGINE] = SET_LIODN_BASE_1(47), #endif +#ifdef CONFIG_SYS_DPAA_RMAN + [FSL_HW_PORTAL_RMAN] = SET_LIODN_BASE_1(80), +#endif }; diff --git a/arch/powerpc/cpu/mpc85xx/portals.c b/arch/powerpc/cpu/mpc85xx/portals.c index 418dd9d9ea..6199633541 100644 --- a/arch/powerpc/cpu/mpc85xx/portals.c +++ b/arch/powerpc/cpu/mpc85xx/portals.c @@ -245,6 +245,12 @@ void fdt_fixup_qportals(void *blob) goto err; } #endif +#ifdef CONFIG_SYS_DPAA_RMAN + err = fdt_qportal(blob, off, i, "rman@0", + FSL_HW_PORTAL_RMAN, 1); + if (err < 0) + goto err; +#endif err: if (err < 0) { diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index c65f76370f..a9973b80da 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -175,12 +175,20 @@ extern void fdt_fixup_liodn(void *blob); offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \ CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) +#define SET_RMAN_LIODN(ibNum, liodn) \ + SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \ + offsetof(struct ccsr_rman, mmitdr) + \ + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \ + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000) + extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; extern struct liodn_id_table raide_liodn_tbl[]; extern struct liodn_id_table fman1_liodn_tbl[], fman2_liodn_tbl[]; extern struct srio_liodn_id_table srio_liodn_tbl[]; +extern struct liodn_id_table rman_liodn_tbl[]; extern int liodn_tbl_sz, sec_liodn_tbl_sz, raide_liodn_tbl_sz; extern int fman1_liodn_tbl_sz, fman2_liodn_tbl_sz; extern int srio_liodn_tbl_sz; +extern int rman_liodn_tbl_sz; #endif diff --git a/arch/powerpc/include/asm/fsl_portals.h b/arch/powerpc/include/asm/fsl_portals.h index 8c3ea0bac4..5644044eb8 100644 --- a/arch/powerpc/include/asm/fsl_portals.h +++ b/arch/powerpc/include/asm/fsl_portals.h @@ -38,6 +38,10 @@ enum fsl_dpaa_dev { #ifdef CONFIG_SYS_FSL_RAID_ENGINE FSL_HW_PORTAL_RAID_ENGINE, #endif +#ifdef CONFIG_SYS_DPAA_RMAN + FSL_HW_PORTAL_RMAN, +#endif + }; struct qportal_info { diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 1bbf9867af..99fe97d087 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2339,6 +2339,16 @@ struct ccsr_raide { }; #endif +#ifdef CONFIG_SYS_DPAA_RMAN +struct ccsr_rman { + u8 res0[0xf64]; + u32 mmliodnbr; /* Message Manager LIODN Base Register */ + u32 mmitar; /* RMAN Inbound Translation Address Register */ + u32 mmitdr; /* RMAN Inbound Translation Data Register */ + u8 res4[0x1f090]; +}; +#endif + #ifdef CONFIG_FSL_CORENET #define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #define CONFIG_SYS_MPC85xx_DDR_OFFSET 0x8000 @@ -2354,6 +2364,7 @@ struct ccsr_raide { #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 #define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 @@ -2442,6 +2453,8 @@ struct ccsr_raide { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) #define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) +#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \ + (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET) #define CONFIG_SYS_MPC85xx_GUTS_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 91c250f05a..337e8df27d 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -66,6 +66,7 @@ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ #define CONFIG_SRIO2 /* SRIO port 2 */ +#define CONFIG_SYS_DPAA_RMAN /* RMan */ #define CONFIG_FSL_LAW /* Use common FSL init code */ diff --git a/include/configs/P3041DS.h b/include/configs/P3041DS.h index e4d1fe5996..57d5de5b12 100644 --- a/include/configs/P3041DS.h +++ b/include/configs/P3041DS.h @@ -35,6 +35,7 @@ #define CONFIG_FSL_SATA_V2 #define CONFIG_PCIE3 #define CONFIG_PCIE4 +#define CONFIG_SYS_DPAA_RMAN #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ diff --git a/include/configs/P5020DS.h b/include/configs/P5020DS.h index 618d1a40fa..a9cee23726 100644 --- a/include/configs/P5020DS.h +++ b/include/configs/P5020DS.h @@ -36,6 +36,7 @@ #define CONFIG_PCIE3 #define CONFIG_PCIE4 #define CONFIG_SYS_FSL_RAID_ENGINE +#define CONFIG_SYS_DPAA_RMAN #define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */ From 2a523f524090d7fc5600ece9f12d7c955db567d7 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 14 Oct 2011 16:26:05 +0800 Subject: [PATCH 06/10] fdt: Add new fdt_set_node_status & fdt_set_status_by_alias helpers Add common function fdt_set_node_status() to assist in various locations that we set a nodes status. This function utilizes the status values that are part of the EPAPR spec (on power.org). fdt_set_status_by_alias() is based on fdt_set_node_status() but uses an alias string to identify the node to update. We also add some shortcut functions to help the common cases of setting "okay" and "disabled": fdt_status_okay() fdt_status_disabled() fdt_status_okay_by_alias() fdt_status_disabled_by_alias() Finally, we fixup the corenet_ds ethernet code which previously had a function by the same name that can be replaced with the new helpers. Signed-off-by: Shengzhou Liu Signed-off-by: Kumar Gala Acked-by: Gerald Van Baren --- board/freescale/corenet_ds/eth_hydra.c | 26 ++--------- board/freescale/corenet_ds/eth_p4080.c | 36 +++++----------- common/fdt_support.c | 60 +++++++++++++++++++++++++- include/fdt_support.h | 28 ++++++++++++ 4 files changed, 101 insertions(+), 49 deletions(-) diff --git a/board/freescale/corenet_ds/eth_hydra.c b/board/freescale/corenet_ds/eth_hydra.c index 91b340826d..a7a5e13af7 100644 --- a/board/freescale/corenet_ds/eth_hydra.c +++ b/board/freescale/corenet_ds/eth_hydra.c @@ -70,6 +70,7 @@ #include #include #include +#include #include #include "../common/ngpixis.h" @@ -199,25 +200,6 @@ static int hydra_mdio_init(char *realbusname, char *fakebusname) return mdio_register(bus); } -/* - * Given an alias or a path for a node, set the status of that node. - * - * If 'alias' is not a valid alias, then it is treated as a full path to the - * node. No error checking is performed. - * - * This function is normally called to set the status for a virtual MDIO node. - */ -static void fdt_set_node_status(void *fdt, const char *alias, - const char *status) -{ - const char *path = fdt_get_alias(fdt, alias); - - if (!path) - path = alias; - - do_fixup_by_path(fdt, path, "status", status, strlen(status) + 1, 1); -} - /* * Given an alias or a path for a node, set the mux value of that node. * @@ -372,14 +354,14 @@ void fdt_fixup_board_enet(void *fdt) case PHY_INTERFACE_MODE_SGMII: lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); if (lane >= 0) { - fdt_set_node_status(fdt, "emi1_sgmii", "okay"); + fdt_status_okay_by_alias(fdt, "emi1_sgmii"); /* Also set the MUX value */ fdt_set_mdio_mux(fdt, "emi1_sgmii", mdio_mux[i].val); } break; case PHY_INTERFACE_MODE_RGMII: - fdt_set_node_status(fdt, "emi1_rgmii", "okay"); + fdt_status_okay_by_alias(fdt, "emi1_rgmii"); break; default: break; @@ -388,7 +370,7 @@ void fdt_fixup_board_enet(void *fdt) lane = serdes_get_first_lane(XAUI_FM1); if (lane >= 0) - fdt_set_node_status(fdt, "emi2_xgmii", "okay"); + fdt_status_okay_by_alias(fdt, "emi2_xgmii"); #endif } diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index d4657f7316..00dfa9ac39 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -199,22 +199,6 @@ static int p4080ds_mdio_init(char *realbusname, u32 muxval) return mdio_register(bus); } -/* - * Sets the specified node's status to the value contained in "status" - * If the first character of the specified path is "/" then we use - * alias as a path. Otherwise, we look for an alias of that name - */ -static void fdt_set_node_status(void *fdt, const char *alias, - const char *status) -{ - const char *path = fdt_get_alias(fdt, alias); - - if (!path) - path = alias; - - do_fixup_by_path(fdt, path, "status", status, strlen(status) + 1, 1); -} - void board_ft_fman_fixup_port(void *blob, char * prop, phys_addr_t pa, enum fm_port port, int offset) { @@ -255,28 +239,28 @@ void fdt_fixup_board_enet(void *fdt) */ /* We've got six MDIO nodes that may or may not need to exist */ - fdt_set_node_status(fdt, "emi1_slot3", "disabled"); - fdt_set_node_status(fdt, "emi1_slot4", "disabled"); - fdt_set_node_status(fdt, "emi1_slot5", "disabled"); - fdt_set_node_status(fdt, "emi2_slot4", "disabled"); - fdt_set_node_status(fdt, "emi2_slot5", "disabled"); + fdt_status_disabled_by_alias(fdt, "emi1_slot3"); + fdt_status_disabled_by_alias(fdt, "emi1_slot4"); + fdt_status_disabled_by_alias(fdt, "emi1_slot5"); + fdt_status_disabled_by_alias(fdt, "emi2_slot4"); + fdt_status_disabled_by_alias(fdt, "emi2_slot5"); for (i = 0; i < NUM_FM_PORTS; i++) { switch (mdio_mux[i]) { case EMI1_SLOT3: - fdt_set_node_status(fdt, "emi1_slot3", "okay"); + fdt_status_okay_by_alias(fdt, "emi1_slot3"); break; case EMI1_SLOT4: - fdt_set_node_status(fdt, "emi1_slot4", "okay"); + fdt_status_okay_by_alias(fdt, "emi1_slot4"); break; case EMI1_SLOT5: - fdt_set_node_status(fdt, "emi1_slot5", "okay"); + fdt_status_okay_by_alias(fdt, "emi1_slot5"); break; case EMI2_SLOT4: - fdt_set_node_status(fdt, "emi2_slot4", "okay"); + fdt_status_okay_by_alias(fdt, "emi2_slot4"); break; case EMI2_SLOT5: - fdt_set_node_status(fdt, "emi2_slot5", "okay"); + fdt_status_okay_by_alias(fdt, "emi2_slot5"); break; } } diff --git a/common/fdt_support.c b/common/fdt_support.c index e0d3fe33e7..bdda64d2d7 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -2,7 +2,7 @@ * (C) Copyright 2007 * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com * - * Copyright 2010 Freescale Semiconductor, Inc. + * Copyright 2010-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -1259,6 +1259,64 @@ unsigned int fdt_create_phandle(void *fdt, int nodeoffset) return phandle; } +/* + * fdt_set_node_status: Set status for the given node + * + * @fdt: ptr to device tree + * @nodeoffset: node to update + * @status: FDT_STATUS_OKAY, FDT_STATUS_DISABLED, + * FDT_STATUS_FAIL, FDT_STATUS_FAIL_ERROR_CODE + * @error_code: optional, only used if status is FDT_STATUS_FAIL_ERROR_CODE + */ +int fdt_set_node_status(void *fdt, int nodeoffset, + enum fdt_status status, unsigned int error_code) +{ + char buf[16]; + int ret = 0; + + if (nodeoffset < 0) + return nodeoffset; + + switch (status) { + case FDT_STATUS_OKAY: + ret = fdt_setprop_string(fdt, nodeoffset, "status", "okay"); + break; + case FDT_STATUS_DISABLED: + ret = fdt_setprop_string(fdt, nodeoffset, "status", "disabled"); + break; + case FDT_STATUS_FAIL: + ret = fdt_setprop_string(fdt, nodeoffset, "status", "fail"); + break; + case FDT_STATUS_FAIL_ERROR_CODE: + sprintf(buf, "fail-%d", error_code); + ret = fdt_setprop_string(fdt, nodeoffset, "status", buf); + break; + default: + printf("Invalid fdt status: %x\n", status); + ret = -1; + break; + } + + return ret; +} + +/* + * fdt_set_status_by_alias: Set status for the given node given an alias + * + * @fdt: ptr to device tree + * @alias: alias of node to update + * @status: FDT_STATUS_OKAY, FDT_STATUS_DISABLED, + * FDT_STATUS_FAIL, FDT_STATUS_FAIL_ERROR_CODE + * @error_code: optional, only used if status is FDT_STATUS_FAIL_ERROR_CODE + */ +int fdt_set_status_by_alias(void *fdt, const char* alias, + enum fdt_status status, unsigned int error_code) +{ + int offset = fdt_path_offset(fdt, alias); + + return fdt_set_node_status(fdt, offset, status, error_code); +} + #if defined(CONFIG_VIDEO) int fdt_add_edid(void *blob, const char *compat, unsigned char *edid_buf) { diff --git a/include/fdt_support.h b/include/fdt_support.h index 4826eee1ba..c7b4605f06 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -104,5 +104,33 @@ int fdt_verify_alias_address(void *fdt, int anode, const char *alias, u64 addr); u64 fdt_get_base_address(void *fdt, int node); +enum fdt_status { + FDT_STATUS_OKAY, + FDT_STATUS_DISABLED, + FDT_STATUS_FAIL, + FDT_STATUS_FAIL_ERROR_CODE, +}; +int fdt_set_node_status(void *fdt, int nodeoffset, + enum fdt_status status, unsigned int error_code); +static inline int fdt_status_okay(void *fdt, int nodeoffset) +{ + return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_OKAY, 0); +} +static inline int fdt_status_disabled(void *fdt, int nodeoffset) +{ + return fdt_set_node_status(fdt, nodeoffset, FDT_STATUS_DISABLED, 0); +} + +int fdt_set_status_by_alias(void *fdt, const char* alias, + enum fdt_status status, unsigned int error_code); +static inline int fdt_status_okay_by_alias(void *fdt, const char* alias) +{ + return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_OKAY, 0); +} +static inline int fdt_status_disabled_by_alias(void *fdt, const char* alias) +{ + return fdt_set_status_by_alias(fdt, alias, FDT_STATUS_DISABLED, 0); +} + #endif /* ifdef CONFIG_OF_LIBFDT */ #endif /* ifndef __FDT_SUPPORT_H */ From f81f19fafaa8e88649e252a6d84096c83e682853 Mon Sep 17 00:00:00 2001 From: Shengzhou Liu Date: Fri, 14 Oct 2011 16:26:06 +0800 Subject: [PATCH 07/10] powerpc/85xx: Update USB device tree status based on pin settings For P3060 and P4080, USB pins are multiplexed with other functions. Update the device tree status for USB ports based on setting of RCW[EC1] & RCW[EC2] which describe if pins are muxed to usb. Signed-off-by: Shengzhou Liu Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/fdt.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 9d2d76956e..9d31568412 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -537,6 +537,27 @@ void fdt_fixup_fman_firmware(void *blob) #define fdt_fixup_fman_firmware(x) #endif +#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060) +static void fdt_fixup_usb(void *fdt) +{ + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + u32 rcwsr11 = in_be32(&gur->rcwsr[11]); + int off; + + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-mph"); + if ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) != + FSL_CORENET_RCWSR11_EC1_FM1_USB1) + fdt_status_disabled(fdt, off); + + off = fdt_node_offset_by_compatible(fdt, -1, "fsl,mpc85xx-usb2-dr"); + if ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) != + FSL_CORENET_RCWSR11_EC2_USB2) + fdt_status_disabled(fdt, off); +} +#else +#define fdt_fixup_usb(x) +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { int off; @@ -641,6 +662,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "fsl,flexcan-v1.0", "clock_freq", gd->bus_clk, 1); + + fdt_fixup_usb(blob); } /* From 3b001ad26d6e03ebe2510ec8506a8425392adcf8 Mon Sep 17 00:00:00 2001 From: Kumar Gala Date: Tue, 18 Oct 2011 01:31:08 -0500 Subject: [PATCH 08/10] powerpc/85xx: Fix P2020DS booting The following commit removed the code that set odt_rd_cfg and odt_wr_cfg. With out this code P2020DS board will not boot: commit 712cf7ab0b58e51a69e339397457d3591b6b650e Author: York Sun Date: Mon Oct 3 09:19:53 2011 -0700 powerpc/mpc8xxx: Merge entries in DDR speed table Signed-off-by: Kumar Gala --- board/freescale/p2020ds/ddr.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/board/freescale/p2020ds/ddr.c b/board/freescale/p2020ds/ddr.c index c43f874c92..59034f9f89 100644 --- a/board/freescale/p2020ds/ddr.c +++ b/board/freescale/p2020ds/ddr.c @@ -57,6 +57,7 @@ void fsl_ddr_board_options(memctl_options_t *popts, { const struct board_specific_parameters *pbsp, *pbsp_highest = NULL; ulong ddr_freq; + int i; if (ctrl_num) { printf("Wrong parameter for controller number %d", ctrl_num); @@ -65,6 +66,17 @@ void fsl_ddr_board_options(memctl_options_t *popts, if (!pdimm->n_ranks) return; + /* + * set odt_rd_cfg and odt_wr_cfg. If the there is only one dimm in + * that controller, set odt_wr_cfg to 4 for CS0, and 0 to CS1. If + * there are two dimms in the controller, set odt_rd_cfg to 3 and + * odt_wr_cfg to 3 for the even CS, 0 for the odd CS. + */ + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = 0; + popts->cs_local_opts[i].odt_wr_cfg = 1; + } + pbsp = dimm0; /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr From a836626cc4ddae53bfa46195a39194f21ad157af Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 18 Oct 2011 18:44:34 -0500 Subject: [PATCH 09/10] powerpc/85xx: wait for alignment before resetting SERDES RX lanes (SERDES9) The work-around for P4080 erratum SERDES9 says that the SERDES receiver lanes should be reset after the XAUI starts tranmitting alignment signals. Signed-off-by: Timur Tabi Signed-off-by: Kumar Gala --- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 10 ----- board/freescale/corenet_ds/eth_p4080.c | 38 +++++++++++++++---- drivers/net/phy/teranetics.c | 2 +- include/phy.h | 4 ++ 4 files changed, 35 insertions(+), 19 deletions(-) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 07e58ed024..89ed5b47fc 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -504,9 +504,6 @@ void fsl_serdes_init(void) const char *srds_lpd_arg; size_t arglen; #endif -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 - enum srds_prtcl device; -#endif #ifdef CONFIG_SYS_P4080_ERRATUM_SERDES_A001 int need_serdes_a001; /* TRUE == need work-around for SERDES A001 */ #endif @@ -787,11 +784,4 @@ void fsl_serdes_init(void) SRDS_RSTCTL_SDPD); } #endif - -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 - for (device = XAUI_FM1; device <= XAUI_FM2; device++) { - if (is_serdes_configured(device)) - __serdes_reset_rx(srds_regs, cfg, device); - } -#endif } diff --git a/board/freescale/corenet_ds/eth_p4080.c b/board/freescale/corenet_ds/eth_p4080.c index 00dfa9ac39..7ff00d1460 100644 --- a/board/freescale/corenet_ds/eth_p4080.c +++ b/board/freescale/corenet_ds/eth_p4080.c @@ -93,21 +93,43 @@ struct mii_dev *mii_dev_for_muxval(u32 muxval) return bus; } -#ifdef CONFIG_SYS_P4080_ERRATUM_SERDES9 +#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9) && defined(CONFIG_PHY_TERANETICS) int board_phy_config(struct phy_device *phydev) { - /* - * If this is the 10G PHY, and we switched it to fiber, - * we need to reset the serdes link for SERDES9 - */ - if ((phydev->port == PORT_FIBRE) && (phydev->drv->uid == 0x00a19410)) { + if (phydev->drv->uid == PHY_UID_TN2020) { + unsigned long timeout = 1 * 1000; /* 1 seconds */ enum srds_prtcl device; + /* + * Wait for the XAUI to come out of reset. This is when it + * starts transmitting alignment signals. + */ + while (--timeout) { + int reg = phy_read(phydev, MDIO_MMD_PHYXS, MDIO_CTRL1); + if (reg < 0) { + printf("TN2020: Error reading from PHY at " + "address %u\n", phydev->addr); + break; + } + /* + * Note that we've never actually seen + * MDIO_CTRL1_RESET set to 1. + */ + if ((reg & MDIO_CTRL1_RESET) == 0) + break; + udelay(1000); + } + + if (!timeout) { + printf("TN2020: Timeout waiting for PHY at address %u " + " to reset.\n", phydev->addr); + } + switch (phydev->addr) { - case 4: + case CONFIG_SYS_FM1_10GEC1_PHY_ADDR: device = XAUI_FM1; break; - case 0: + case CONFIG_SYS_FM2_10GEC1_PHY_ADDR: device = XAUI_FM2; break; default: diff --git a/drivers/net/phy/teranetics.c b/drivers/net/phy/teranetics.c index 9d9397aadd..78447b711f 100644 --- a/drivers/net/phy/teranetics.c +++ b/drivers/net/phy/teranetics.c @@ -95,7 +95,7 @@ int tn2020_startup(struct phy_device *phydev) struct phy_driver tn2020_driver = { .name = "Teranetics TN2020", - .uid = 0x00a19410, + .uid = PHY_UID_TN2020, .mask = 0xfffffff0, .features = PHY_10G_FEATURES, .mmds = (MDIO_DEVS_PMAPMD | MDIO_DEVS_PCS | diff --git a/include/phy.h b/include/phy.h index d5817bf19f..095f41c43b 100644 --- a/include/phy.h +++ b/include/phy.h @@ -226,4 +226,8 @@ int phy_natsemi_init(void); int phy_realtek_init(void); int phy_teranetics_init(void); int phy_vitesse_init(void); + +/* PHY UIDs for various PHYs that are referenced in external code */ +#define PHY_UID_TN2020 0x00a19410 + #endif From 710308ee185b3087e474fb9b205f47613c65dda4 Mon Sep 17 00:00:00 2001 From: Kyle Moffett Date: Wed, 19 Oct 2011 14:58:15 -0400 Subject: [PATCH 10/10] mpc85xx: Add inline GPIO acessor functions To ease the implementation of other MPC85xx board ports, several common GPIO helpers are added to . Since each of these compiles to no more than 4-5 instructions it would be very inefficient to call them out of line, therefore we put them entirely in the header file. The HWW-1U-1A board port which these were written for strongly prefers to set multiple GPIOs as a single batch operation, so the API is designed around that basis. To assist other board ports, a small set of wrappers are used which provides a standard gpio_request() interface around the MPC85xx-specific functions. This can be enabled with CONFIG_MPC85XX_GENERIC_GPIO Signed-off-by: Kyle Moffett Cc: Andy Fleming Cc: Peter Tyser Signed-off-by: Kumar Gala --- arch/powerpc/include/asm/mpc85xx_gpio.h | 123 ++++++++++++++++++++++++ 1 file changed, 123 insertions(+) create mode 100644 arch/powerpc/include/asm/mpc85xx_gpio.h diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h new file mode 100644 index 0000000000..5a608a5d0f --- /dev/null +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h @@ -0,0 +1,123 @@ +/* + * Copyright 2010 eXMeritus, A Boeing Company + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef POWERPC_ASM_MPC85XX_GPIO_H_ +#define POWERPC_ASM_MPC85XX_GPIO_H_ + +# include + +/* + * The following internal functions are an MPC85XX-specific GPIO API which + * allows setting and querying multiple GPIOs in a single operation. + * + * All of these look relatively large, but the arguments are almost always + * constants, so they compile down to just a few instructions and a + * memory-mapped IO operation or two. + */ +static inline void mpc85xx_gpio_set(unsigned int mask, + unsigned int dir, unsigned int val) +{ + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + + /* First mask off the unwanted parts of "dir" and "val" */ + dir &= mask; + val &= mask; + + /* Now read in the values we're supposed to preserve */ + dir |= (in_be32(&gpio->gpdir) & ~mask); + val |= (in_be32(&gpio->gpdat) & ~mask); + + /* + * Poke the new output values first, then set the direction. This + * helps to avoid transient data when switching from input to output + * and vice versa. + */ + out_be32(&gpio->gpdat, val); + out_be32(&gpio->gpdir, dir); +} + +static inline void mpc85xx_gpio_set_in(unsigned int gpios) +{ + mpc85xx_gpio_set(gpios, 0x00000000, 0x00000000); +} + +static inline void mpc85xx_gpio_set_low(unsigned int gpios) +{ + mpc85xx_gpio_set(gpios, 0xFFFFFFFF, 0x00000000); +} + +static inline void mpc85xx_gpio_set_high(unsigned int gpios) +{ + mpc85xx_gpio_set(gpios, 0xFFFFFFFF, 0xFFFFFFFF); +} + +static inline unsigned int mpc85xx_gpio_get(unsigned int mask) +{ + ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + 0xc00); + + /* Read the requested values */ + return in_be32(&gpio->gpdat) & mask; +} + +/* + * These implement the generic Linux GPIO API on top of the other functions + * in this header. + */ +static inline int gpio_request(unsigned gpio, const char *label) +{ + /* Compatibility shim */ + return 0; +} + +static inline void gpio_free(unsigned gpio) +{ + /* Compatibility shim */ +} + +static inline int gpio_direction_input(unsigned gpio) +{ + mpc85xx_gpio_set_in(1U << gpio); + return 0; +} + +static inline int gpio_direction_output(unsigned gpio, int value) +{ + mpc85xx_gpio_set_low(1U << gpio); + return 0; +} + +static inline int gpio_get_value(unsigned gpio) +{ + return !!mpc85xx_gpio_get(1U << gpio); +} + +static inline void gpio_set_value(unsigned gpio, int value) +{ + if (value) + mpc85xx_gpio_set_high(1U << gpio); + else + mpc85xx_gpio_set_low(1U << gpio); +} + +static inline int gpio_is_valid(int gpio) +{ + return (gpio >= 0) && (gpio < 32); +} + +#endif /* not POWERPC_ASM_MPC85XX_GPIO_H_ */