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ehci-fsl: correct size of ehci caplength

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According to the EHCI specification the Capability Register Length
has a size of 8 bits.

Signed-off-by: Wolfgang Grandegger <wg@denx.de>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Wolfgang Grandegger 2011-10-17 20:16:09 +02:00 committed by Remy Bohmer
parent 7555d5ec29
commit 0255f2d87c
1 changed files with 13 additions and 12 deletions
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25
include/usb/ehci-fsl.h
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@ -186,35 +186,36 @@ struct usb_ehci {
u32 gptimer1_ctrl; /* 0x08C - General Purpose Timer 1 control */
u32 sbuscfg; /* 0x090 - System Bus Interface Control */
u8 res2[0x6C];
u16 caplength; /* 0x100 - Capability Register Length */
u8 caplength; /* 0x100 - Capability Register Length */
u8 res3[0x1];
u16 hciversion; /* 0x102 - Host Interface Version */
u32 hcsparams; /* 0x104 - Host Structural Parameters */
u32 hccparams; /* 0x108 - Host Capability Parameters */
u8 res3[0x14];
u8 res4[0x14];
u32 dciversion; /* 0x120 - Device Interface Version */
u32 dciparams; /* 0x124 - Device Controller Params */
u8 res4[0x18];
u8 res5[0x18];
u32 usbcmd; /* 0x140 - USB Command */
u32 usbsts; /* 0x144 - USB Status */
u32 usbintr; /* 0x148 - USB Interrupt Enable */
u32 frindex; /* 0x14C - USB Frame Index */
u8 res5[0x4];
u8 res6[0x4];
u32 perlistbase; /* 0x154 - Periodic List Base
- USB Device Address */
u32 ep_list_addr; /* 0x158 - Next Asynchronous List
- End Point Address */
u8 res6[0x4];
u8 res7[0x4];
u32 burstsize; /* 0x160 - Programmable Burst Size */
#define FSL_EHCI_TXPBURST(X) ((X) << 8)
#define FSL_EHCI_RXPBURST(X) (X)
u32 txfilltuning; /* 0x164 - Host TT Transmit
pre-buffer packet tuning */
u8 res7[0x8];
u8 res8[0x8];
u32 ulpi_viewpoint; /* 0x170 - ULPI Reister Access */
u8 res8[0xc];
u8 res9[0xc];
u32 config_flag; /* 0x180 - Configured Flag Register */
u32 portsc; /* 0x184 - Port status/control */
u8 res9[0x1C];
u8 res10[0x1C];
u32 otgsc; /* 0x1a4 - Oo-The-Go status and control */
u32 usbmode; /* 0x1a8 - USB Device Mode */
u32 epsetupstat; /* 0x1ac - End Point Setup Status */
@ -228,18 +229,18 @@ struct usb_ehci {
u32 epctrl3; /* 0x1cc - End Point Control 3 */
u32 epctrl4; /* 0x1d0 - End Point Control 4 */
u32 epctrl5; /* 0x1d4 - End Point Control 5 */
u8 res10[0x28];
u8 res11[0x28];
u32 usbgenctrl; /* 0x200 - USB General Control */
u32 isiphyctrl; /* 0x204 - On-Chip PHY Control */
u8 res11[0x1F8];
u8 res12[0x1F8];
u32 snoop1; /* 0x400 - Snoop 1 */
u32 snoop2; /* 0x404 - Snoop 2 */
u32 age_cnt_limit; /* 0x408 - Age Count Threshold */
u32 prictrl; /* 0x40c - Priority Control */
u32 sictrl; /* 0x410 - System Interface Control */
u8 res12[0xEC];
u8 res13[0xEC];
u32 control; /* 0x500 - Control */
u8 res13[0xafc];
u8 res14[0xafc];
};
#endif /* _EHCI_FSL_H */