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arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT support
Add support for selecting the appropriate DTS file depending on the SERDES protocol used. The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS file specifically made for the current SERDES protocol. This patch adds the necessary DPMAC nodes (DPMAC 1-8) for protocol 42 (0x2A) on SD#1. Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled implement the board_fit_config_name_match() function in order to choose the appropriate DTS. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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@ -374,6 +374,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
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ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
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ls1021a-iot-duart.dtb ls1021a-tsn.dtb
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dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
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fsl-ls2080a-qds-42-x.dtb \
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fsl-ls2080a-rdb.dtb \
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fsl-ls2081a-rdb.dtb \
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fsl-ls2088a-rdb-qspi.dtb \
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16
arch/arm/dts/fsl-ls2080a-qds-42-x.dts
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16
arch/arm/dts/fsl-ls2080a-qds-42-x.dts
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@ -0,0 +1,16 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LS2080AQDS device tree source for SERDES protocol 42.x
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*
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* Copyright 2020 NXP
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*
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*/
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/dts-v1/;
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#include "fsl-ls2080a-qds-sd1-42.dtsi"
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/ {
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model = "NXP Layerscape LS2080AQDS Board (DTS 42-x)";
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compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
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};
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48
arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
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48
arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi
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@ -0,0 +1,48 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* NXP LS2080aQDS device tree source for SERDES block #1 - protocol 42 (0x2a)
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*
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* Copyright 2020 NXP
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*/
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#include "fsl-ls2080a-qds.dtsi"
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&dpmac1 {
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status = "okay";
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phy-connection-type = "xfi";
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};
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&dpmac2 {
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status = "okay";
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phy-connection-type = "xfi";
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};
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&dpmac3 {
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status = "okay";
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phy-connection-type = "xfi";
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};
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&dpmac4 {
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status = "okay";
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phy-connection-type = "xfi";
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};
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&dpmac5 {
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status = "okay";
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phy-connection-type = "xfi";
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};
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&dpmac6 {
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status = "okay";
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phy-connection-type = "xfi";
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};
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&dpmac7 {
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status = "okay";
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phy-connection-type = "xfi";
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};
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&dpmac8 {
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status = "okay";
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phy-connection-type = "xfi";
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};
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@ -1,13 +1,13 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Freescale ls2080a QDS board device tree source
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* Freescale ls2080a QDS defaul board device tree source
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*
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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*/
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/dts-v1/;
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#include "fsl-ls2080a.dtsi"
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#include "fsl-ls2080a-qds.dtsi"
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/ {
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model = "Freescale Layerscape 2080a QDS Board";
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@ -18,71 +18,3 @@
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spi1 = &dspi;
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};
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};
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&i2c0 {
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status = "okay";
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pca9547@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00>;
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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};
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};
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};
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};
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&dspi {
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bus-num = <0>;
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status = "okay";
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dflash0: n25q128a {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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dflash1: sst25wf040b {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <1>;
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};
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dflash2: en25s64 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <2>;
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};
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};
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&qspi {
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status = "okay";
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s25fs256s0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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};
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&sata {
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status = "okay";
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};
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77
arch/arm/dts/fsl-ls2080a-qds.dtsi
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77
arch/arm/dts/fsl-ls2080a-qds.dtsi
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@ -0,0 +1,77 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/*
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* Freescale ls2080a QDS common device tree source
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*
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* Copyright 2013-2015 Freescale Semiconductor, Inc.
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* Copyright 2020 NXP
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*/
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#include "fsl-ls2080a.dtsi"
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&i2c0 {
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status = "okay";
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pca9547@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00>;
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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};
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};
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};
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};
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&dspi {
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bus-num = <0>;
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status = "okay";
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dflash0: n25q128a {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <0>;
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};
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dflash1: sst25wf040b {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <1>;
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};
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dflash2: en25s64 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <3000000>;
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spi-cpol;
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spi-cpha;
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reg = <2>;
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};
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};
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&qspi {
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status = "okay";
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s25fs256s0: flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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};
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&sata {
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status = "okay";
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};
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@ -989,3 +989,100 @@ void reset_phy(void)
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mc_env_boot();
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}
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#endif /* CONFIG_RESET_PHY_R */
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#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
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/* Structure to hold SERDES protocols supported in case of
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* CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
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*
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* @serdes_block: the index of the SERDES block
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* @serdes_protocol: the decimal value of the protocol supported
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* @dts_needed: DTS notes describing the current configuration are needed
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*
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* When dts_needed is true, the board_fit_config_name_match() function
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* will try to exactly match the current configuration of the block with a DTS
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* name provided.
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*/
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static struct serdes_configuration {
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u8 serdes_block;
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u32 serdes_protocol;
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bool dts_needed;
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} supported_protocols[] = {
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/* Serdes block #1 */
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{1, 42, true},
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/* Serdes block #2 */
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{2, 65, false},
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};
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#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
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static bool protocol_supported(u8 serdes_block, u32 protocol)
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{
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struct serdes_configuration serdes_conf;
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int i;
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for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
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serdes_conf = supported_protocols[i];
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if (serdes_conf.serdes_block == serdes_block &&
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serdes_conf.serdes_protocol == protocol)
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return true;
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}
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return false;
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}
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static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
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{
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struct serdes_configuration serdes_conf;
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int i;
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for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
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serdes_conf = supported_protocols[i];
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if (serdes_conf.serdes_block == serdes_block &&
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serdes_conf.serdes_protocol == protocol) {
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if (serdes_conf.dts_needed == true)
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sprintf(str, "%u", protocol);
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else
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sprintf(str, "x");
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return;
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}
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}
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}
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int board_fit_config_name_match(const char *name)
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{
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struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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u32 rcw_status = in_le32(&gur->rcwsr[28]);
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char srds_s1_str[2], srds_s2_str[2];
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u32 srds_s1, srds_s2;
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char expected_dts[100];
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srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
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srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
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srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
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srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
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/* Check for supported protocols. The default DTS will be used
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* in this case
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*/
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if (!protocol_supported(1, srds_s1) ||
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!protocol_supported(2, srds_s2))
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return -1;
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get_str_protocol(1, srds_s1, srds_s1_str);
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get_str_protocol(2, srds_s2, srds_s2_str);
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printf("expected_dts %s\n", expected_dts);
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sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s",
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srds_s1_str, srds_s2_str);
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if (!strcmp(name, expected_dts))
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return 0;
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printf("this is not!\n");
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return -1;
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}
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#endif
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