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arm: dts: ls2080aqds: add CONFIG_MULTI_DTB_FIT support

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Add support for selecting the appropriate DTS file depending on the
SERDES protocol used.

The fsl-ls2080a-qds DTS will be used by default if there isn't a DTS
file specifically made for the current SERDES protocol.

This patch adds the necessary DPMAC nodes (DPMAC 1-8) for
protocol 42 (0x2A) on SD#1.

Also, in case CONFIG_DM_ETH and CONFIG_MULTI_DTB_FIT are enabled
implement the board_fit_config_name_match() function in order to choose
the appropriate DTS.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Ioana Ciornei 2020-05-18 14:48:36 +03:00 committed by Priyanka Jain
parent 8cbef912ee
commit 020ed9c666
6 changed files with 241 additions and 70 deletions
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1
arch/arm/dts/Makefile
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@ -374,6 +374,7 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \
ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \
ls1021a-iot-duart.dtb ls1021a-tsn.dtb
dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
fsl-ls2080a-qds-42-x.dtb \
fsl-ls2080a-rdb.dtb \
fsl-ls2081a-rdb.dtb \
fsl-ls2088a-rdb-qspi.dtb \

16
arch/arm/dts/fsl-ls2080a-qds-42-x.dts Normal file
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@ -0,0 +1,16 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS2080AQDS device tree source for SERDES protocol 42.x
*
* Copyright 2020 NXP
*
*/
/dts-v1/;
#include "fsl-ls2080a-qds-sd1-42.dtsi"
/ {
model = "NXP Layerscape LS2080AQDS Board (DTS 42-x)";
compatible = "fsl,ls2080a-qds", "fsl,ls2080a";
};

48
arch/arm/dts/fsl-ls2080a-qds-sd1-42.dtsi Normal file
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@ -0,0 +1,48 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP LS2080aQDS device tree source for SERDES block #1 - protocol 42 (0x2a)
*
* Copyright 2020 NXP
*/
#include "fsl-ls2080a-qds.dtsi"
&dpmac1 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac2 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac3 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac4 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac5 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac6 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac7 {
status = "okay";
phy-connection-type = "xfi";
};
&dpmac8 {
status = "okay";
phy-connection-type = "xfi";
};

72
arch/arm/dts/fsl-ls2080a-qds.dts
View File

@ -1,13 +1,13 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Freescale ls2080a QDS board device tree source
* Freescale ls2080a QDS defaul board device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
*/
/dts-v1/;
#include "fsl-ls2080a.dtsi"
#include "fsl-ls2080a-qds.dtsi"
/ {
model = "Freescale Layerscape 2080a QDS Board";
@ -18,71 +18,3 @@
spi1 = &dspi;
};
};
&i2c0 {
status = "okay";
pca9547@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
};
};
&dspi {
bus-num = <0>;
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};
&qspi {
status = "okay";
s25fs256s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&sata {
status = "okay";
};

77
arch/arm/dts/fsl-ls2080a-qds.dtsi Normal file
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@ -0,0 +1,77 @@
// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* Freescale ls2080a QDS common device tree source
*
* Copyright 2013-2015 Freescale Semiconductor, Inc.
* Copyright 2020 NXP
*/
#include "fsl-ls2080a.dtsi"
&i2c0 {
status = "okay";
pca9547@77 {
compatible = "nxp,pca9547";
reg = <0x77>;
#address-cells = <1>;
#size-cells = <0>;
i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00>;
rtc@68 {
compatible = "dallas,ds3232";
reg = <0x68>;
};
};
};
};
&dspi {
bus-num = <0>;
status = "okay";
dflash0: n25q128a {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <0>;
};
dflash1: sst25wf040b {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <1>;
};
dflash2: en25s64 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <3000000>;
spi-cpol;
spi-cpha;
reg = <2>;
};
};
&qspi {
status = "okay";
s25fs256s0: flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
reg = <0>;
};
};
&sata {
status = "okay";
};

97
board/freescale/ls2080aqds/eth.c
View File

@ -989,3 +989,100 @@ void reset_phy(void)
mc_env_boot();
}
#endif /* CONFIG_RESET_PHY_R */
#if defined(CONFIG_DM_ETH) && defined(CONFIG_MULTI_DTB_FIT)
/* Structure to hold SERDES protocols supported in case of
* CONFIG_DM_ETH enabled (network interfaces are described in the DTS).
*
* @serdes_block: the index of the SERDES block
* @serdes_protocol: the decimal value of the protocol supported
* @dts_needed: DTS notes describing the current configuration are needed
*
* When dts_needed is true, the board_fit_config_name_match() function
* will try to exactly match the current configuration of the block with a DTS
* name provided.
*/
static struct serdes_configuration {
u8 serdes_block;
u32 serdes_protocol;
bool dts_needed;
} supported_protocols[] = {
/* Serdes block #1 */
{1, 42, true},
/* Serdes block #2 */
{2, 65, false},
};
#define SUPPORTED_SERDES_PROTOCOLS ARRAY_SIZE(supported_protocols)
static bool protocol_supported(u8 serdes_block, u32 protocol)
{
struct serdes_configuration serdes_conf;
int i;
for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
serdes_conf = supported_protocols[i];
if (serdes_conf.serdes_block == serdes_block &&
serdes_conf.serdes_protocol == protocol)
return true;
}
return false;
}
static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
{
struct serdes_configuration serdes_conf;
int i;
for (i = 0; i < SUPPORTED_SERDES_PROTOCOLS; i++) {
serdes_conf = supported_protocols[i];
if (serdes_conf.serdes_block == serdes_block &&
serdes_conf.serdes_protocol == protocol) {
if (serdes_conf.dts_needed == true)
sprintf(str, "%u", protocol);
else
sprintf(str, "x");
return;
}
}
}
int board_fit_config_name_match(const char *name)
{
struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
u32 rcw_status = in_le32(&gur->rcwsr[28]);
char srds_s1_str[2], srds_s2_str[2];
u32 srds_s1, srds_s2;
char expected_dts[100];
srds_s1 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
srds_s2 = rcw_status & FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
/* Check for supported protocols. The default DTS will be used
* in this case
*/
if (!protocol_supported(1, srds_s1) ||
!protocol_supported(2, srds_s2))
return -1;
get_str_protocol(1, srds_s1, srds_s1_str);
get_str_protocol(2, srds_s2, srds_s2_str);
printf("expected_dts %s\n", expected_dts);
sprintf(expected_dts, "fsl-ls2080a-qds-%s-%s",
srds_s1_str, srds_s2_str);
if (!strcmp(name, expected_dts))
return 0;
printf("this is not!\n");
return -1;
}
#endif