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driver/ddr/fsl: Add workaround for erratum A-010165

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During DDR-2133 operation, the transmit data eye margins determined
during the memory controller initialization may be sub-optimal, set
DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Shengzhou Liu 2016-05-10 16:03:47 +08:00 committed by York Sun
parent 397b0d9e29
commit 019a147b65
2 changed files with 10 additions and 1 deletions
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1
arch/arm/include/asm/arch-fsl-layerscape/config.h
View File

@ -137,6 +137,7 @@
#define CONFIG_SYS_FSL_ERRATUM_A009801
#define CONFIG_SYS_FSL_ERRATUM_A009803
#define CONFIG_SYS_FSL_ERRATUM_A009942
#define CONFIG_SYS_FSL_ERRATUM_A010165
/* ARM A57 CORE ERRATA */
#define CONFIG_ARM_ERRATA_826974

10
drivers/ddr/fsl/fsl_ddr_gen4.c
View File

@ -56,7 +56,8 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
u32 vref_seq2[3] = {0xc0, 0xf0, 0x70}; /* for range 2 */
u32 *vref_seq = vref_seq1;
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A009942
#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) | \
defined(CONFIG_SYS_FSL_ERRATUM_A010165)
ulong ddr_freq;
u32 tmp;
#endif
@ -271,6 +272,13 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
ddr_out32(&ddr->debug[28], tmp | 0x0060007b);
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A010165
ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
if ((ddr_freq > 1900) && (ddr_freq < 2300)) {
tmp = ddr_in32(&ddr->debug[28]);
ddr_out32(&ddr->debug[28], tmp | 0x000a0000);
}
#endif
/*
* For RDIMMs, JEDEC spec requires clocks to be stable before reset is
* deasserted. Clocks start when any chip select is enabled and clock