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watchdog: Add booke watchdog driver
Add a driver for the PowerPC Book E watchdog driver that is present on a number of Freescale/NXP SoCs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
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@ -124,6 +124,13 @@ config WDT_BCM6345
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The watchdog timer is stopped when initialized.
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The watchdog timer is stopped when initialized.
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It performs full SoC reset.
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It performs full SoC reset.
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config WDT_BOOKE
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bool "PowerPC Book-E watchdog driver"
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depends on WDT && MPC85xx
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help
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Watchdog driver for PowerPC Book-E chips, such as the Freescale
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MPC85xx SOCs and the IBM PowerPC 440.
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config WDT_CDNS
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config WDT_CDNS
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bool "Cadence watchdog timer support"
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bool "Cadence watchdog timer support"
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depends on WDT
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depends on WDT
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@ -21,6 +21,7 @@ obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
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obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
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obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
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obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
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obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
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obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
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obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
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obj-$(CONFIG_WDT_BOOKE) += booke_wdt.o
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obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
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obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
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obj-$(CONFIG_WDT_ORION) += orion_wdt.o
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obj-$(CONFIG_WDT_ORION) += orion_wdt.o
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obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
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obj-$(CONFIG_WDT_CDNS) += cdns_wdt.o
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106
drivers/watchdog/booke_wdt.c
Normal file
106
drivers/watchdog/booke_wdt.c
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@ -0,0 +1,106 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Watchdog timer for PowerPC Book-E systems
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*/
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#include <div64.h>
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#include <dm.h>
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#include <wdt.h>
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#include <asm/processor.h>
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#define WDTP_MASK TCR_WP(0x3f)
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/* For the specified period, determine the number of seconds
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* corresponding to the reset time. There will be a watchdog
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* exception at approximately 3/5 of this time.
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*
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* The formula to calculate this is given by:
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* 2.5 * (2^(63-period+1)) / timebase_freq
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*
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* In order to simplify things, we assume that period is
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* at least 1. This will still result in a very long timeout.
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*/
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static unsigned long long period_to_sec(unsigned int period)
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{
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unsigned long long tmp = 1ULL << (64 - period);
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unsigned long tmp2 = get_tbclk();
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/* tmp may be a very large number and we don't want to overflow,
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* so divide the timebase freq instead of multiplying tmp
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*/
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tmp2 = tmp2 / 5 * 2;
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do_div(tmp, tmp2);
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return tmp;
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}
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/*
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* This procedure will find the highest period which will give a timeout
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* greater than the one required. e.g. for a bus speed of 66666666 and
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* and a parameter of 2 secs, then this procedure will return a value of 38.
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*/
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static unsigned int sec_to_period(unsigned int secs)
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{
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unsigned int period;
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for (period = 63; period > 0; period--) {
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if (period_to_sec(period) >= secs)
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return period;
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}
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return 0;
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}
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static int booke_wdt_reset(struct udevice *dev)
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{
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mtspr(SPRN_TSR, TSR_ENW | TSR_WIS);
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return 0;
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}
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static int booke_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
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{
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u32 val;
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unsigned int timeout = DIV_ROUND_UP(timeout_ms, 1000);
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/* clear status before enabling watchdog */
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booke_wdt_reset(dev);
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val = mfspr(SPRN_TCR);
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val &= ~WDTP_MASK;
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val |= (TCR_WIE | TCR_WRC(WRC_CHIP) | TCR_WP(sec_to_period(timeout)));
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mtspr(SPRN_TCR, val);
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return 0;
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}
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static int booke_wdt_stop(struct udevice *dev)
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{
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u32 val;
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val = mfspr(SPRN_TCR);
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val &= ~(TCR_WIE | WDTP_MASK);
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mtspr(SPRN_TCR, val);
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/* clear status to make sure nothing is pending */
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booke_wdt_reset(dev);
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return 0;
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}
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static const struct wdt_ops booke_wdt_ops = {
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.start = booke_wdt_start,
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.stop = booke_wdt_stop,
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.reset = booke_wdt_reset,
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};
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static const struct udevice_id booke_wdt_ids[] = {
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{ .compatible = "fsl,booke-wdt" },
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{}
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};
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U_BOOT_DRIVER(booke_wdt) = {
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.name = "booke_wdt",
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.id = UCLASS_WDT,
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.of_match = booke_wdt_ids,
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.ops = &booke_wdt_ops,
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};
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