brain-hackers_pepepper-mirror
/
u-boot-brain
mirror of https://github.com/brain-hackers/u-boot-brain
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
u-boot-brain/arch/x86/cpu/u-boot-spl.lds

104 lines
2.1 KiB
Plaintext
Raw Normal View History

SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
2018-05-07 06:58:06 +09:00
/* SPDX-License-Identifier: GPL-2.0+ */
x86: Add a link script for SPL If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 23:04:02 +09:00
/*
* (C) Copyright 2002
* Daniel Engström, Omicron Ceti AB, daniel@omicron.se.
*/
#include <config.h>
OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
OUTPUT_ARCH(i386)
ENTRY(_start)
SECTIONS
{
#ifndef CONFIG_CMDLINE
/DISCARD/ : { *(.u_boot_list_2_cmd_*) }
#endif
linker: Modify linker scripts to be more generic Make use of "IMAGE_MAX_SIZE" and "IMAGE_TEXT_BASE" rather than CONFIG_SPL_MAX_SIZE and CONFIG_SPL_TEXT_BASE. This lets us re-use the same script for both SPL and TPL. Add logic to scripts/Makefile.spl to pass in the right value when preprocessing the script. Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: Jagan Teki <jagan@openedev.com> Cc: Maxime Ripard <maxime.ripard@bootlin.com> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: York Sun <york.sun@nxp.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Heiko Schocher <hs@denx.de> Cc: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Tested-by: Adam Ford <aford173@gmail.com> #da850evm & omap3_logic_somlv Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
2019-01-23 07:09:26 +09:00
. = IMAGE_TEXT_BASE; /* Location of bootcode in flash */
x86: Add a link script for SPL If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 23:04:02 +09:00
__text_start = .;
x86: Define the SPL image start Define this symbol so that we can use binman symbols correctly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-12-07 13:42:00 +09:00
.text : {
__image_copy_start = .;
*(.text*);
}
x86: Add a link script for SPL If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 23:04:02 +09:00
. = ALIGN(4);
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
x86: Define a region for device priv/plat data Collect this together in one place, so driver model can access set it up in a new place if needed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
2021-03-15 13:25:44 +09:00
. = ALIGN(4);
.priv_data : {
__priv_data_start = .;
*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.priv_data*)))
__priv_data_end = .;
}
x86: Add a link script for SPL If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 23:04:02 +09:00
. = ALIGN(4);
.data : { *(.data*) }
. = ALIGN(4);
__data_end = .;
__init_end = .;
x86: Add binman symbols to the image It is useful in SPL and TPL to access symbols from binman, such as the position and size of an entry in the ROM. Collect these symbols together in the SPL binaries. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-25 23:11:36 +09:00
. = ALIGN(4);
.binman_sym_table : {
__binman_sym_start = .;
KEEP(*(SORT(.binman_sym*)));
__binman_sym_end = .;
x86: Make sure the SPL image ends on a suitable boundary The part of U-Boot that actually ends up in u-boot-nodtb.bin is not built with any particular alignment. It ends at the start of the BSS section. The BSS section selects its own alignment, which may larger. This means that there can be a gap of a few bytes between the image ending and BSS starting. Since u-boot.bin is build by joining u-boot-nodtb.bin and u-boot.dtb (with perhaps some padding for BSS), the expected result is not obtained. U-Boot uses the end of BSS to find the devicetree, so this means that it cannot be found. Add 32-byte alignment of BSS so that the image size is correct and appending the devicetree will place it at the end of BSS. Example SPL output without this patch: Sections: Idx Name Size VMA LMA File off Algn 0 .text 000142a1 fef40000 fef40000 00001000 2**4 CONTENTS, ALLOC, LOAD, RELOC, READONLY, CODE 1 .u_boot_list 000014a4 fef542a8 fef542a8 000152a8 2**3 CONTENTS, ALLOC, LOAD, RELOC, DATA 2 .rodata 0000599c fef55760 fef55760 00016760 2**5 CONTENTS, ALLOC, LOAD, RELOC, READONLY, DATA 3 .data 00000970 fef5b100 fef5b100 0001c100 2**5 CONTENTS, ALLOC, LOAD, RELOC, DATA 4 .binman_sym_table 00000020 fef5ba70 fef5ba70 0001ca70 2**2 CONTENTS, ALLOC, LOAD, DATA 5 .bss 00000060 fef5baa0 fef5baa0 00000000 2**5 ALLOC You can see that .bss is aligned to 2**5 (32 bytes). This is because of the mallinfo struct in dlmalloc.c: 17 .bss.current_mallinfo 00000028 00000000 00000000 000004c0 2**5 ALLOC In this case the size of u-boot-spl-nodtb.bin is 0x1ba90. This matches up with the _image_binary_end symbol: fef5ba90 g .binman_sym_table 00000000 _image_binary_end But BSS starts 16 bytes later, at 0xfef5baa0, due to the 32-byte alignment. So we must align _image_binary_end to a 32-byte boundary. This forces the binary size to be 0x1baa0, i.e. ending at the start of bss, as expected. Note that gcc reports __BIGGEST_ALIGNMENT__ of 16 on this build, even though it generates an object file with a member that requests 32-byte alignment. The current_mallinfo struct is 40 bytes in size. Increasing the struct to 68 bytes (i.e. just above a 64-byte boundary) does not cause the alignment to go above 32 bytes. So it seems that 32 bytes is the maximum alignment at present. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: add more details in the commit message to help people understand] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
2021-01-25 02:06:05 +09:00
/*
* Force 32-byte alignment so that it lines up with the start of
* bss, which may have up to 32-byte alignment. This ensures
* that the end of the .bin file matches up with
* _image_binary_end or __bss_end - see board_fdt_blob_setup().
* The alignment of BSS depends on what is in it, so can range
* from 4 to 32 bytes.
*/
. = ALIGN(32);
x86: Add binman symbols to the image It is useful in SPL and TPL to access symbols from binman, such as the position and size of an entry in the ROM. Collect these symbols together in the SPL binaries. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-25 23:11:36 +09:00
}
x86: Add a link script for SPL If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 23:04:02 +09:00
_image_binary_end = .;
x86: spl: Make moving BSS conditional At present BSS is always placed in SDRAM. If a separate BSS is not in use this means that BSS doesn't work as expected. Make the setting conditional on the SEPARATE_BSS option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-01-25 02:06:06 +09:00
#if CONFIG_IS_ENABLED(SEPARATE_BSS)
x86: Add a link script for SPL If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 23:04:02 +09:00
. = 0x120000;
x86: spl: Make moving BSS conditional At present BSS is always placed in SDRAM. If a separate BSS is not in use this means that BSS doesn't work as expected. Make the setting conditional on the SEPARATE_BSS option. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2021-01-25 02:06:06 +09:00
#endif
x86: Add a link script for SPL If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 23:04:02 +09:00
.bss (OVERLAY) : {
__bss_start = .;
*(.bss*)
*(COM*)
. = ALIGN(4);
__bss_end = .;
}
__bss_size = __bss_end - __bss_start;
/DISCARD/ : { *(.dynstr*) }
/DISCARD/ : { *(.dynamic*) }
/DISCARD/ : { *(.plt*) }
/DISCARD/ : { *(.interp*) }
/DISCARD/ : { *(.gnu*) }
x86: Discard .note.gnu.property sections When switching to kernel.org x86_64 gcc 11.1.0 toolchain, u-boot.rom built from qemu-x86_defconfig no longer boots anymore. Investigation shows that U-Boot fails at a very early stage during the boot process, in fdtdec_prepare_fdt() where fdt_check_header() complains that there is not a valid device tree found at gd->fdt_blob which points to _end. Now _end points to an allocated section .note.gnu.property which of course is wrong. This issue is however not seen when using the default Ubuntu 20.04 gnu toolchain (gcc 9.3.0 with binutils 2.34). Further investigation shows that it is caused by a behavior change of binutils v2.36 which is part of the kernel.org gcc 11.1.0 toolchain, via the following commit: 939b95c77bf2 ("Linux/x86: Configure gas with --enable-x86-used-note by default") In fact, there was already a regression bug report [1] for binutils two months ago, but the binutils folks did not think it is a bug :( To resolve this, there are several options: * pass -Wa,-mx86-used-note=no to gas * pass -R .note.gnu.property to objcopy * discard the section in the linker script Linux kernel uses the discard way [2], so let's do the same for U-Boot. [1] https://sourceware.org/bugzilla/show_bug.cgi?id=27753 [2] commit 4caffe6a28d3 ("x86/vdso: Discard .note.gnu.property sections in vDSO") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
2021-06-18 16:09:30 +09:00
/DISCARD/ : { *(.note.gnu.property) }
x86: Add a link script for SPL If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 23:04:02 +09:00
x86: Allow 16-bit init to be in TPL At present we support having 16-bit init be in SPL or U-Boot proper, but not TPL. Add support for this so that TPL can boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-04-26 12:58:53 +09:00
#if defined(CONFIG_SPL_X86_16BIT_INIT) || defined(CONFIG_TPL_X86_16BIT_INIT)
x86: Add a link script for SPL If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2017-01-16 23:04:02 +09:00
/*
* The following expressions place the 16-bit Real-Mode code and
* Reset Vector at the end of the Flash ROM
*/
. = START_16 - RESET_SEG_START;
.start16 : AT (START_16) {
KEEP(*(.start16));
}
. = RESET_VEC_LOC - RESET_SEG_START;
.resetvec : AT (RESET_VEC_LOC) {
KEEP(*(.resetvec));
}
#endif
}