2013-02-04 20:38:59 +09:00
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/*
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* Copyright (c) 2013 Xilinx Inc.
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*
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2013-07-08 16:37:19 +09:00
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* SPDX-License-Identifier: GPL-2.0+
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2013-02-04 20:38:59 +09:00
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*/
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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extern void zynq_slcr_lock(void);
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extern void zynq_slcr_unlock(void);
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extern void zynq_slcr_cpu_reset(void);
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2013-11-22 06:39:01 +09:00
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extern void zynq_slcr_gem_clk_setup(u32 gem_id, unsigned long clk_rate);
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2013-04-22 22:43:02 +09:00
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extern void zynq_slcr_devcfg_disable(void);
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extern void zynq_slcr_devcfg_enable(void);
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2014-01-09 05:18:21 +09:00
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extern u32 zynq_slcr_get_boot_mode(void);
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2013-04-22 22:43:02 +09:00
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extern u32 zynq_slcr_get_idcode(void);
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2014-04-25 19:21:04 +09:00
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extern int zynq_slcr_get_mio_pin_status(const char *periph);
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2013-06-17 21:37:01 +09:00
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extern void zynq_ddrc_init(void);
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2013-11-29 22:31:25 +09:00
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extern unsigned int zynq_get_silicon_version(void);
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2013-02-04 20:38:59 +09:00
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2013-04-22 21:56:49 +09:00
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/* Driver extern functions */
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extern int zynq_sdhci_init(u32 regbase);
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2014-02-24 19:16:31 +09:00
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extern int zynq_sdhci_of_init(const void *blob);
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2013-04-22 21:56:49 +09:00
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2013-02-04 20:38:59 +09:00
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#endif /* _SYS_PROTO_H_ */
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