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https://github.com/brain-hackers/u-boot-brain
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194 lines
4.9 KiB
C
194 lines
4.9 KiB
C
![]() |
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Rockchip Electronics Co., Ltd
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*/
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#include <common.h>
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#include <dm.h>
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#include <dm/pinctrl.h>
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#include <regmap.h>
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#include <syscon.h>
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#include "pinctrl-rockchip.h"
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static struct rockchip_mux_route_data rk3399_mux_route_data[] = {
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{
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/* uart2dbga_rx */
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.bank_num = 4,
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.pin = 8,
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.func = 2,
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.route_offset = 0xe21c,
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.route_val = BIT(16 + 10) | BIT(16 + 11),
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}, {
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/* uart2dbgb_rx */
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.bank_num = 4,
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.pin = 16,
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.func = 2,
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.route_offset = 0xe21c,
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.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(10),
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}, {
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/* uart2dbgc_rx */
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.bank_num = 4,
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.pin = 19,
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.func = 1,
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.route_offset = 0xe21c,
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.route_val = BIT(16 + 10) | BIT(16 + 11) | BIT(11),
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}, {
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/* pcie_clkreqn */
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.bank_num = 2,
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.pin = 26,
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.func = 2,
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.route_offset = 0xe21c,
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.route_val = BIT(16 + 14),
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}, {
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/* pcie_clkreqnb */
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.bank_num = 4,
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.pin = 24,
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.func = 1,
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.route_offset = 0xe21c,
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.route_val = BIT(16 + 14) | BIT(14),
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},
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};
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#define RK3399_PULL_GRF_OFFSET 0xe040
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#define RK3399_PULL_PMU_OFFSET 0x40
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static void rk3399_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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/* The bank0:16 and bank1:32 pins are located in PMU */
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if (bank->bank_num == 0 || bank->bank_num == 1) {
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*regmap = priv->regmap_pmu;
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*reg = RK3399_PULL_PMU_OFFSET;
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*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
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*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
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*bit = pin_num % ROCKCHIP_PULL_PINS_PER_REG;
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*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
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} else {
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*regmap = priv->regmap_base;
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*reg = RK3399_PULL_GRF_OFFSET;
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/* correct the offset, as we're starting with the 3rd bank */
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*reg -= 0x20;
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*reg += bank->bank_num * ROCKCHIP_PULL_BANK_STRIDE;
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*reg += ((pin_num / ROCKCHIP_PULL_PINS_PER_REG) * 4);
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*bit = (pin_num % ROCKCHIP_PULL_PINS_PER_REG);
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*bit *= ROCKCHIP_PULL_BITS_PER_PIN;
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}
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}
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static void rk3399_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
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int pin_num, struct regmap **regmap,
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int *reg, u8 *bit)
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{
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struct rockchip_pinctrl_priv *priv = bank->priv;
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int drv_num = (pin_num / 8);
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/* The bank0:16 and bank1:32 pins are located in PMU */
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if (bank->bank_num == 0 || bank->bank_num == 1)
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*regmap = priv->regmap_pmu;
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else
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*regmap = priv->regmap_base;
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*reg = bank->drv[drv_num].offset;
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if (bank->drv[drv_num].drv_type == DRV_TYPE_IO_1V8_3V0_AUTO ||
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bank->drv[drv_num].drv_type == DRV_TYPE_IO_3V3_ONLY)
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*bit = (pin_num % 8) * 3;
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else
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*bit = (pin_num % 8) * 2;
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}
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static struct rockchip_pin_bank rk3399_pin_banks[] = {
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PIN_BANK_IOMUX_FLAGS_DRV_FLAGS_OFFSET_PULL_FLAGS(0, 32, "gpio0",
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_DEFAULT,
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DRV_TYPE_IO_DEFAULT,
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0x80,
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0x88,
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-1,
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-1,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_DEFAULT,
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PULL_TYPE_IO_DEFAULT
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),
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PIN_BANK_IOMUX_DRV_FLAGS_OFFSET(1, 32, "gpio1", IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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IOMUX_SOURCE_PMU,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0,
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0xa0,
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0xa8,
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0xb0,
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0xb8
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),
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PIN_BANK_DRV_FLAGS_PULL_FLAGS(2, 32, "gpio2", DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_ONLY,
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DRV_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_DEFAULT,
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PULL_TYPE_IO_DEFAULT,
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PULL_TYPE_IO_1V8_ONLY,
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PULL_TYPE_IO_1V8_ONLY
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),
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PIN_BANK_DRV_FLAGS(3, 32, "gpio3", DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_IO_3V3_ONLY,
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DRV_TYPE_IO_1V8_OR_3V0
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),
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PIN_BANK_DRV_FLAGS(4, 32, "gpio4", DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_3V0_AUTO,
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DRV_TYPE_IO_1V8_OR_3V0,
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DRV_TYPE_IO_1V8_OR_3V0
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),
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};
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static struct rockchip_pin_ctrl rk3399_pin_ctrl = {
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.pin_banks = rk3399_pin_banks,
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.nr_banks = ARRAY_SIZE(rk3399_pin_banks),
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.label = "RK3399-GPIO",
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.type = RK3399,
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.grf_mux_offset = 0xe000,
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.pmu_mux_offset = 0x0,
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.grf_drv_offset = 0xe100,
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.pmu_drv_offset = 0x80,
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.iomux_routes = rk3399_mux_route_data,
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.niomux_routes = ARRAY_SIZE(rk3399_mux_route_data),
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.pull_calc_reg = rk3399_calc_pull_reg_and_bit,
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.drv_calc_reg = rk3399_calc_drv_reg_and_bit,
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};
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static const struct udevice_id rk3399_pinctrl_ids[] = {
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{
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.compatible = "rockchip,rk3399-pinctrl",
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.data = (ulong)&rk3399_pin_ctrl
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},
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{ }
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};
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U_BOOT_DRIVER(pinctrl_rk3399) = {
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.name = "rockchip_rk3399_pinctrl",
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.id = UCLASS_PINCTRL,
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.of_match = rk3399_pinctrl_ids,
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.priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
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.ops = &rockchip_pinctrl_ops,
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#if !CONFIG_IS_ENABLED(OF_PLATDATA)
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.bind = dm_scan_fdt_dev,
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#endif
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.probe = rockchip_pinctrl_probe,
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};
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