mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 01:48:52 +09:00
125 lines
3.4 KiB
C
125 lines
3.4 KiB
C
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/*
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* Copyright (C) 2016 Socionext Inc.
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*/
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#include <common.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <asm/processor.h>
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#include "../init.h"
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#include "umc64-regs.h"
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#define CONFIG_DDR_FREQ 1866
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#define DRAM_CH_NR 2
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enum dram_freq {
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DRAM_FREQ_1600M,
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DRAM_FREQ_NR,
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};
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enum dram_size {
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DRAM_SZ_256M,
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DRAM_SZ_512M,
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DRAM_SZ_NR,
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};
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/* umc */
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static u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
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static u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
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static u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
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static u32 umc_cmdctle[DRAM_FREQ_NR] = {0x0078071D};
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static u32 umc_cmdctlf[DRAM_FREQ_NR] = {0x02000200};
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static u32 umc_cmdctlg[DRAM_FREQ_NR] = {0x08080808};
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static u32 umc_rdatactl_d0[DRAM_FREQ_NR] = {0x00000810};
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static u32 umc_rdatactl_d1[DRAM_FREQ_NR] = {0x00000810};
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static u32 umc_wdatactl_d0[DRAM_FREQ_NR] = {0x00000004};
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static u32 umc_wdatactl_d1[DRAM_FREQ_NR] = {0x00000004};
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static u32 umc_odtctl_d0[DRAM_FREQ_NR] = {0x02000002};
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static u32 umc_odtctl_d1[DRAM_FREQ_NR] = {0x02000002};
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static u32 umc_acssetb[DRAM_CH_NR] = {0x00000200, 0x00000203};
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static u32 umc_memconfch[DRAM_FREQ_NR] = {0x00023605};
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static int umc_dc_init(void __iomem *dc_base, enum dram_freq freq,
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unsigned long size, int ch)
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{
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writel(umc_cmdctla[freq], dc_base + UMC_CMDCTLA);
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writel(umc_cmdctlb[freq], dc_base + UMC_CMDCTLB);
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writel(umc_cmdctlc[freq], dc_base + UMC_CMDCTLC);
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writel(umc_cmdctle[freq], dc_base + UMC_CMDCTLE);
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writel(umc_cmdctlf[freq], dc_base + UMC_CMDCTLF);
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writel(umc_cmdctlg[freq], dc_base + UMC_CMDCTLG);
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writel(umc_rdatactl_d0[freq], dc_base + UMC_RDATACTL_D0);
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writel(umc_rdatactl_d1[freq], dc_base + UMC_RDATACTL_D1);
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writel(umc_wdatactl_d0[freq], dc_base + UMC_WDATACTL_D0);
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writel(umc_wdatactl_d1[freq], dc_base + UMC_WDATACTL_D1);
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writel(umc_odtctl_d0[freq], dc_base + UMC_ODTCTL_D0);
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writel(umc_odtctl_d1[freq], dc_base + UMC_ODTCTL_D1);
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writel(0x00000003, dc_base + UMC_ACSSETA);
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writel(0x00000103, dc_base + UMC_FLOWCTLG);
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writel(umc_acssetb[ch], dc_base + UMC_ACSSETB);
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writel(0x02020200, dc_base + UMC_SPCSETB);
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writel(umc_memconfch[freq], dc_base + UMC_MEMCONFCH);
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writel(0x00000002, dc_base + UMC_ACFETCHCTRL);
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return 0;
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}
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static int umc_ch_init(void __iomem *umc_ch_base,
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enum dram_freq freq, unsigned long size, int ch)
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{
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void __iomem *dc_base = umc_ch_base;
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return umc_dc_init(dc_base, freq, size, ch);
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}
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static void um_init(void __iomem *um_base)
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{
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writel(0x00000001, um_base + UMC_SIORST);
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writel(0x00000001, um_base + UMC_VO0RST);
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writel(0x00000001, um_base + UMC_VPERST);
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writel(0x00000001, um_base + UMC_RGLRST);
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writel(0x00000001, um_base + UMC_A2DRST);
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writel(0x00000001, um_base + UMC_DMDRST);
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}
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int uniphier_ld11_umc_init(const struct uniphier_board_data *bd)
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{
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void __iomem *um_base = (void __iomem *)0x5B800000;
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void __iomem *umc_ch_base = (void __iomem *)0x5BC00000;
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enum dram_freq freq;
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int ch, ret;
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switch (bd->dram_freq) {
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case 1600:
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freq = DRAM_FREQ_1600M;
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break;
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default:
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pr_err("unsupported DRAM frequency %d MHz\n", bd->dram_freq);
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return -EINVAL;
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}
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for (ch = 0; ch < bd->dram_nr_ch; ch++) {
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unsigned long size = bd->dram_ch[ch].size;
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unsigned int width = bd->dram_ch[ch].width;
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ret = umc_ch_init(umc_ch_base, freq, size / (width / 16), ch);
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if (ret) {
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pr_err("failed to initialize UMC ch%d\n", ch);
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return ret;
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}
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umc_ch_base += 0x00200000;
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}
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um_init(um_base);
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return 0;
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}
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