u-boot-brain/arch/arm/dts/r8a77965-u-boot.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source extras for U-Boot on RCar R8A77965 SoC
 *
 * Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
 */

#include "r8a779x-u-boot.dtsi"

&extalr_clk {
	u-boot,dm-pre-reloc;
};

&soc {
	rpc: rpc@0xee200000 {
		compatible = "renesas,rpc-r8a77965", "renesas,rpc";
		reg = <0 0xee200000 0 0x100>, <0 0x08000000 0 0>;
		clocks = <&cpg CPG_MOD 917>;
		bank-width = <2>;
		status = "disabled";
	};

	ehci0: usb@ee080100 {
		compatible = "generic-ehci";
		reg = <0 0xee080100 0 0x100>;
		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg CPG_MOD 703>;
		phys = <&usb2_phy0>;
		phy-names = "usb";
		companion= <&ohci0>;
		power-domains = <&sysc 32>;
		resets = <&cpg 703>;
	};

	usb2_phy0: usb-phy@ee080200 {
		compatible = "renesas,usb2-phy-r8a77965",
			     "renesas,rcar-gen3-usb2-phy";
		reg = <0 0xee080200 0 0x700>;
		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg CPG_MOD 703>;
		power-domains = <&sysc 32>;
		resets = <&cpg 703>;
		#phy-cells = <0>;
	};

	ehci1: usb@ee0a0100 {
		compatible = "generic-ehci";
		reg = <0 0xee0a0100 0 0x100>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg CPG_MOD 702>;
		phys = <&usb2_phy1>;
		phy-names = "usb";
		companion= <&ohci1>;
		power-domains = <&sysc 32>;
		resets = <&cpg 702>;
	};

	usb2_phy1: usb-phy@ee0a0200 {
		compatible = "renesas,usb2-phy-r8a77965",
			     "renesas,rcar-gen3-usb2-phy";
		reg = <0 0xee0a0200 0 0x700>;
		clocks = <&cpg CPG_MOD 702>;
		power-domains = <&sysc 32>;
		resets = <&cpg 702>;
		#phy-cells = <0>;
	};

	xhci0: usb@ee000000 {
		compatible = "renesas,xhci-r8a77965",
			     "renesas,rcar-gen3-xhci";
		reg = <0 0xee000000 0 0xc00>;
		interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg CPG_MOD 328>;
		power-domains = <&sysc 32>;
		resets = <&cpg 328>;
	};
};