mirror of
https://github.com/brain-hackers/u-boot-brain
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537 lines
15 KiB
C
537 lines
15 KiB
C
![]() |
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Atmel QSPI Controller
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*
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* Copyright (C) 2015 Atmel Corporation
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* Copyright (C) 2018 Cryptera A/S
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*
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* Author: Cyrille Pitchen <cyrille.pitchen@atmel.com>
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* Author: Piotr Bugalski <bugalski.piotr@gmail.com>
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*/
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#include <asm/io.h>
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <fdtdec.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/ioport.h>
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#include <mach/clk.h>
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#include <spi.h>
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#include <spi-mem.h>
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/* QSPI register offsets */
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#define QSPI_CR 0x0000 /* Control Register */
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#define QSPI_MR 0x0004 /* Mode Register */
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#define QSPI_RD 0x0008 /* Receive Data Register */
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#define QSPI_TD 0x000c /* Transmit Data Register */
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#define QSPI_SR 0x0010 /* Status Register */
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#define QSPI_IER 0x0014 /* Interrupt Enable Register */
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#define QSPI_IDR 0x0018 /* Interrupt Disable Register */
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#define QSPI_IMR 0x001c /* Interrupt Mask Register */
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#define QSPI_SCR 0x0020 /* Serial Clock Register */
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#define QSPI_IAR 0x0030 /* Instruction Address Register */
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#define QSPI_ICR 0x0034 /* Instruction Code Register */
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#define QSPI_WICR 0x0034 /* Write Instruction Code Register */
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#define QSPI_IFR 0x0038 /* Instruction Frame Register */
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#define QSPI_RICR 0x003C /* Read Instruction Code Register */
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#define QSPI_SMR 0x0040 /* Scrambling Mode Register */
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#define QSPI_SKR 0x0044 /* Scrambling Key Register */
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#define QSPI_WPMR 0x00E4 /* Write Protection Mode Register */
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#define QSPI_WPSR 0x00E8 /* Write Protection Status Register */
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#define QSPI_VERSION 0x00FC /* Version Register */
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/* Bitfields in QSPI_CR (Control Register) */
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#define QSPI_CR_QSPIEN BIT(0)
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#define QSPI_CR_QSPIDIS BIT(1)
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#define QSPI_CR_SWRST BIT(7)
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#define QSPI_CR_LASTXFER BIT(24)
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/* Bitfields in QSPI_MR (Mode Register) */
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#define QSPI_MR_SMM BIT(0)
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#define QSPI_MR_LLB BIT(1)
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#define QSPI_MR_WDRBT BIT(2)
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#define QSPI_MR_SMRM BIT(3)
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#define QSPI_MR_CSMODE_MASK GENMASK(5, 4)
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#define QSPI_MR_CSMODE_NOT_RELOADED (0 << 4)
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#define QSPI_MR_CSMODE_LASTXFER (1 << 4)
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#define QSPI_MR_CSMODE_SYSTEMATICALLY (2 << 4)
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#define QSPI_MR_NBBITS_MASK GENMASK(11, 8)
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#define QSPI_MR_NBBITS(n) ((((n) - 8) << 8) & QSPI_MR_NBBITS_MASK)
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#define QSPI_MR_DLYBCT_MASK GENMASK(23, 16)
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#define QSPI_MR_DLYBCT(n) (((n) << 16) & QSPI_MR_DLYBCT_MASK)
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#define QSPI_MR_DLYCS_MASK GENMASK(31, 24)
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#define QSPI_MR_DLYCS(n) (((n) << 24) & QSPI_MR_DLYCS_MASK)
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/* Bitfields in QSPI_SR/QSPI_IER/QSPI_IDR/QSPI_IMR */
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#define QSPI_SR_RDRF BIT(0)
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#define QSPI_SR_TDRE BIT(1)
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#define QSPI_SR_TXEMPTY BIT(2)
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#define QSPI_SR_OVRES BIT(3)
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#define QSPI_SR_CSR BIT(8)
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#define QSPI_SR_CSS BIT(9)
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#define QSPI_SR_INSTRE BIT(10)
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#define QSPI_SR_QSPIENS BIT(24)
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#define QSPI_SR_CMD_COMPLETED (QSPI_SR_INSTRE | QSPI_SR_CSR)
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/* Bitfields in QSPI_SCR (Serial Clock Register) */
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#define QSPI_SCR_CPOL BIT(0)
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#define QSPI_SCR_CPHA BIT(1)
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#define QSPI_SCR_SCBR_MASK GENMASK(15, 8)
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#define QSPI_SCR_SCBR(n) (((n) << 8) & QSPI_SCR_SCBR_MASK)
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#define QSPI_SCR_DLYBS_MASK GENMASK(23, 16)
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#define QSPI_SCR_DLYBS(n) (((n) << 16) & QSPI_SCR_DLYBS_MASK)
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/* Bitfields in QSPI_ICR (Read/Write Instruction Code Register) */
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#define QSPI_ICR_INST_MASK GENMASK(7, 0)
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#define QSPI_ICR_INST(inst) (((inst) << 0) & QSPI_ICR_INST_MASK)
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#define QSPI_ICR_OPT_MASK GENMASK(23, 16)
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#define QSPI_ICR_OPT(opt) (((opt) << 16) & QSPI_ICR_OPT_MASK)
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/* Bitfields in QSPI_IFR (Instruction Frame Register) */
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#define QSPI_IFR_WIDTH_MASK GENMASK(2, 0)
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#define QSPI_IFR_WIDTH_SINGLE_BIT_SPI (0 << 0)
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#define QSPI_IFR_WIDTH_DUAL_OUTPUT (1 << 0)
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#define QSPI_IFR_WIDTH_QUAD_OUTPUT (2 << 0)
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#define QSPI_IFR_WIDTH_DUAL_IO (3 << 0)
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#define QSPI_IFR_WIDTH_QUAD_IO (4 << 0)
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#define QSPI_IFR_WIDTH_DUAL_CMD (5 << 0)
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#define QSPI_IFR_WIDTH_QUAD_CMD (6 << 0)
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#define QSPI_IFR_INSTEN BIT(4)
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#define QSPI_IFR_ADDREN BIT(5)
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#define QSPI_IFR_OPTEN BIT(6)
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#define QSPI_IFR_DATAEN BIT(7)
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#define QSPI_IFR_OPTL_MASK GENMASK(9, 8)
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#define QSPI_IFR_OPTL_1BIT (0 << 8)
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#define QSPI_IFR_OPTL_2BIT (1 << 8)
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#define QSPI_IFR_OPTL_4BIT (2 << 8)
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#define QSPI_IFR_OPTL_8BIT (3 << 8)
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#define QSPI_IFR_ADDRL BIT(10)
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#define QSPI_IFR_TFRTYP_MEM BIT(12)
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#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
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#define QSPI_IFR_CRM BIT(14)
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#define QSPI_IFR_NBDUM_MASK GENMASK(20, 16)
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#define QSPI_IFR_NBDUM(n) (((n) << 16) & QSPI_IFR_NBDUM_MASK)
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#define QSPI_IFR_APBTFRTYP_READ BIT(24) /* Defined in SAM9X60 */
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/* Bitfields in QSPI_SMR (Scrambling Mode Register) */
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#define QSPI_SMR_SCREN BIT(0)
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#define QSPI_SMR_RVDIS BIT(1)
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/* Bitfields in QSPI_WPMR (Write Protection Mode Register) */
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#define QSPI_WPMR_WPEN BIT(0)
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#define QSPI_WPMR_WPKEY_MASK GENMASK(31, 8)
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#define QSPI_WPMR_WPKEY(wpkey) (((wpkey) << 8) & QSPI_WPMR_WPKEY_MASK)
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/* Bitfields in QSPI_WPSR (Write Protection Status Register) */
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#define QSPI_WPSR_WPVS BIT(0)
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#define QSPI_WPSR_WPVSRC_MASK GENMASK(15, 8)
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#define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
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struct atmel_qspi_caps {
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bool has_qspick;
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bool has_ricr;
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};
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struct atmel_qspi {
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void __iomem *regs;
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void __iomem *mem;
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const struct atmel_qspi_caps *caps;
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ulong bus_clk_rate;
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u32 mr;
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};
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struct atmel_qspi_mode {
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u8 cmd_buswidth;
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u8 addr_buswidth;
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u8 data_buswidth;
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u32 config;
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};
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static const struct atmel_qspi_mode atmel_qspi_modes[] = {
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{ 1, 1, 1, QSPI_IFR_WIDTH_SINGLE_BIT_SPI },
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{ 1, 1, 2, QSPI_IFR_WIDTH_DUAL_OUTPUT },
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{ 1, 1, 4, QSPI_IFR_WIDTH_QUAD_OUTPUT },
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{ 1, 2, 2, QSPI_IFR_WIDTH_DUAL_IO },
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{ 1, 4, 4, QSPI_IFR_WIDTH_QUAD_IO },
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{ 2, 2, 2, QSPI_IFR_WIDTH_DUAL_CMD },
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{ 4, 4, 4, QSPI_IFR_WIDTH_QUAD_CMD },
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};
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static inline bool atmel_qspi_is_compatible(const struct spi_mem_op *op,
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const struct atmel_qspi_mode *mode)
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{
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if (op->cmd.buswidth != mode->cmd_buswidth)
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return false;
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if (op->addr.nbytes && op->addr.buswidth != mode->addr_buswidth)
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return false;
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if (op->data.nbytes && op->data.buswidth != mode->data_buswidth)
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return false;
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return true;
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}
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static int atmel_qspi_find_mode(const struct spi_mem_op *op)
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{
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u32 i;
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for (i = 0; i < ARRAY_SIZE(atmel_qspi_modes); i++)
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if (atmel_qspi_is_compatible(op, &atmel_qspi_modes[i]))
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return i;
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return -ENOTSUPP;
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}
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static bool atmel_qspi_supports_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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if (atmel_qspi_find_mode(op) < 0)
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return false;
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/* special case not supported by hardware */
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if (op->addr.nbytes == 2 && op->cmd.buswidth != op->addr.buswidth &&
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op->dummy.nbytes == 0)
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return false;
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return true;
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}
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static int atmel_qspi_set_cfg(struct atmel_qspi *aq,
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const struct spi_mem_op *op, u32 *offset)
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{
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u32 iar, icr, ifr;
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u32 dummy_cycles = 0;
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int mode;
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iar = 0;
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icr = QSPI_ICR_INST(op->cmd.opcode);
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ifr = QSPI_IFR_INSTEN;
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mode = atmel_qspi_find_mode(op);
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if (mode < 0)
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return mode;
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ifr |= atmel_qspi_modes[mode].config;
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if (op->dummy.buswidth && op->dummy.nbytes)
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dummy_cycles = op->dummy.nbytes * 8 / op->dummy.buswidth;
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/*
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* The controller allows 24 and 32-bit addressing while NAND-flash
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* requires 16-bit long. Handling 8-bit long addresses is done using
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* the option field. For the 16-bit addresses, the workaround depends
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* of the number of requested dummy bits. If there are 8 or more dummy
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* cycles, the address is shifted and sent with the first dummy byte.
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* Otherwise opcode is disabled and the first byte of the address
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* contains the command opcode (works only if the opcode and address
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* use the same buswidth). The limitation is when the 16-bit address is
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* used without enough dummy cycles and the opcode is using a different
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* buswidth than the address.
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*/
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if (op->addr.buswidth) {
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switch (op->addr.nbytes) {
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case 0:
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break;
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case 1:
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ifr |= QSPI_IFR_OPTEN | QSPI_IFR_OPTL_8BIT;
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icr |= QSPI_ICR_OPT(op->addr.val & 0xff);
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break;
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case 2:
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if (dummy_cycles < 8 / op->addr.buswidth) {
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ifr &= ~QSPI_IFR_INSTEN;
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ifr |= QSPI_IFR_ADDREN;
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iar = (op->cmd.opcode << 16) |
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(op->addr.val & 0xffff);
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} else {
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ifr |= QSPI_IFR_ADDREN;
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iar = (op->addr.val << 8) & 0xffffff;
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dummy_cycles -= 8 / op->addr.buswidth;
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}
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break;
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case 3:
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ifr |= QSPI_IFR_ADDREN;
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iar = op->addr.val & 0xffffff;
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break;
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case 4:
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ifr |= QSPI_IFR_ADDREN | QSPI_IFR_ADDRL;
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iar = op->addr.val & 0x7ffffff;
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break;
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default:
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return -ENOTSUPP;
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}
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}
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/* offset of the data access in the QSPI memory space */
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*offset = iar;
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/* Set number of dummy cycles */
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if (dummy_cycles)
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ifr |= QSPI_IFR_NBDUM(dummy_cycles);
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/* Set data enable */
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if (op->data.nbytes)
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ifr |= QSPI_IFR_DATAEN;
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/*
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* If the QSPI controller is set in regular SPI mode, set it in
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* Serial Memory Mode (SMM).
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*/
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if (aq->mr != QSPI_MR_SMM) {
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writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
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aq->mr = QSPI_MR_SMM;
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}
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/* Clear pending interrupts */
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(void)readl(aq->regs + QSPI_SR);
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if (aq->caps->has_ricr) {
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if (!op->addr.nbytes && op->data.dir == SPI_MEM_DATA_IN)
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ifr |= QSPI_IFR_APBTFRTYP_READ;
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/* Set QSPI Instruction Frame registers */
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writel(iar, aq->regs + QSPI_IAR);
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if (op->data.dir == SPI_MEM_DATA_IN)
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writel(icr, aq->regs + QSPI_RICR);
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else
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writel(icr, aq->regs + QSPI_WICR);
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writel(ifr, aq->regs + QSPI_IFR);
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} else {
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if (op->data.dir == SPI_MEM_DATA_OUT)
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ifr |= QSPI_IFR_SAMA5D2_WRITE_TRSFR;
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/* Set QSPI Instruction Frame registers */
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writel(iar, aq->regs + QSPI_IAR);
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writel(icr, aq->regs + QSPI_ICR);
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writel(ifr, aq->regs + QSPI_IFR);
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}
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return 0;
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}
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static int atmel_qspi_exec_op(struct spi_slave *slave,
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const struct spi_mem_op *op)
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{
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struct atmel_qspi *aq = dev_get_priv(slave->dev->parent);
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u32 sr, imr, offset;
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int err;
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err = atmel_qspi_set_cfg(aq, op, &offset);
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if (err)
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return err;
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/* Skip to the final steps if there is no data */
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if (op->data.nbytes) {
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/* Dummy read of QSPI_IFR to synchronize APB and AHB accesses */
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(void)readl(aq->regs + QSPI_IFR);
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/* Send/Receive data */
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if (op->data.dir == SPI_MEM_DATA_IN)
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memcpy_fromio(op->data.buf.in, aq->mem + offset,
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op->data.nbytes);
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else
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memcpy_toio(aq->mem + offset, op->data.buf.out,
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op->data.nbytes);
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/* Release the chip-select */
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writel(QSPI_CR_LASTXFER, aq->regs + QSPI_CR);
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}
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/* Poll INSTruction End and Chip Select Rise flags. */
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imr = QSPI_SR_INSTRE | QSPI_SR_CSR;
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return readl_poll_timeout(aq->regs + QSPI_SR, sr, (sr & imr) == imr,
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1000000);
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}
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static int atmel_qspi_set_speed(struct udevice *bus, uint hz)
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{
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struct atmel_qspi *aq = dev_get_priv(bus);
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u32 scr, scbr, mask, new_value;
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/* Compute the QSPI baudrate */
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scbr = DIV_ROUND_UP(aq->bus_clk_rate, hz);
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if (scbr > 0)
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scbr--;
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new_value = QSPI_SCR_SCBR(scbr);
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mask = QSPI_SCR_SCBR_MASK;
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scr = readl(aq->regs + QSPI_SCR);
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if ((scr & mask) == new_value)
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return 0;
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scr = (scr & ~mask) | new_value;
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writel(scr, aq->regs + QSPI_SCR);
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return 0;
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}
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static int atmel_qspi_set_mode(struct udevice *bus, uint mode)
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{
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struct atmel_qspi *aq = dev_get_priv(bus);
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|
u32 scr, mask, new_value = 0;
|
||
|
|
||
|
if (mode & SPI_CPOL)
|
||
|
new_value = QSPI_SCR_CPOL;
|
||
|
if (mode & SPI_CPHA)
|
||
|
new_value = QSPI_SCR_CPHA;
|
||
|
|
||
|
mask = QSPI_SCR_CPOL | QSPI_SCR_CPHA;
|
||
|
|
||
|
scr = readl(aq->regs + QSPI_SCR);
|
||
|
if ((scr & mask) == new_value)
|
||
|
return 0;
|
||
|
|
||
|
scr = (scr & ~mask) | new_value;
|
||
|
writel(scr, aq->regs + QSPI_SCR);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static int atmel_qspi_enable_clk(struct udevice *dev)
|
||
|
{
|
||
|
struct atmel_qspi *aq = dev_get_priv(dev);
|
||
|
struct clk pclk, qspick;
|
||
|
int ret;
|
||
|
|
||
|
ret = clk_get_by_name(dev, "pclk", &pclk);
|
||
|
if (ret)
|
||
|
ret = clk_get_by_index(dev, 0, &pclk);
|
||
|
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Missing QSPI peripheral clock\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = clk_enable(&pclk);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Failed to enable QSPI peripheral clock\n");
|
||
|
goto free_pclk;
|
||
|
}
|
||
|
|
||
|
if (aq->caps->has_qspick) {
|
||
|
/* Get the QSPI system clock */
|
||
|
ret = clk_get_by_name(dev, "qspick", &qspick);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Missing QSPI peripheral clock\n");
|
||
|
goto free_pclk;
|
||
|
}
|
||
|
|
||
|
ret = clk_enable(&qspick);
|
||
|
if (ret)
|
||
|
dev_err(dev, "Failed to enable QSPI system clock\n");
|
||
|
clk_free(&qspick);
|
||
|
}
|
||
|
|
||
|
aq->bus_clk_rate = clk_get_rate(&pclk);
|
||
|
if (!aq->bus_clk_rate)
|
||
|
ret = -EINVAL;
|
||
|
|
||
|
free_pclk:
|
||
|
clk_free(&pclk);
|
||
|
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static void atmel_qspi_init(struct atmel_qspi *aq)
|
||
|
{
|
||
|
/* Reset the QSPI controller */
|
||
|
writel(QSPI_CR_SWRST, aq->regs + QSPI_CR);
|
||
|
|
||
|
/* Set the QSPI controller by default in Serial Memory Mode */
|
||
|
writel(QSPI_MR_SMM, aq->regs + QSPI_MR);
|
||
|
aq->mr = QSPI_MR_SMM;
|
||
|
|
||
|
/* Enable the QSPI controller */
|
||
|
writel(QSPI_CR_QSPIEN, aq->regs + QSPI_CR);
|
||
|
}
|
||
|
|
||
|
static int atmel_qspi_probe(struct udevice *dev)
|
||
|
{
|
||
|
struct atmel_qspi *aq = dev_get_priv(dev);
|
||
|
struct resource res;
|
||
|
int ret;
|
||
|
|
||
|
aq->caps = (struct atmel_qspi_caps *)dev_get_driver_data(dev);
|
||
|
if (!aq->caps) {
|
||
|
dev_err(dev, "Could not retrieve QSPI caps\n");
|
||
|
return -EINVAL;
|
||
|
};
|
||
|
|
||
|
/* Map the registers */
|
||
|
ret = dev_read_resource_byname(dev, "qspi_base", &res);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "missing registers\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
aq->regs = devm_ioremap(dev, res.start, resource_size(&res));
|
||
|
if (IS_ERR(aq->regs))
|
||
|
return PTR_ERR(aq->regs);
|
||
|
|
||
|
/* Map the AHB memory */
|
||
|
ret = dev_read_resource_byname(dev, "qspi_mmap", &res);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "missing AHB memory\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
aq->mem = devm_ioremap(dev, res.start, resource_size(&res));
|
||
|
if (IS_ERR(aq->mem))
|
||
|
return PTR_ERR(aq->mem);
|
||
|
|
||
|
ret = atmel_qspi_enable_clk(dev);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
atmel_qspi_init(aq);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static const struct spi_controller_mem_ops atmel_qspi_mem_ops = {
|
||
|
.supports_op = atmel_qspi_supports_op,
|
||
|
.exec_op = atmel_qspi_exec_op,
|
||
|
};
|
||
|
|
||
|
static const struct dm_spi_ops atmel_qspi_ops = {
|
||
|
.set_speed = atmel_qspi_set_speed,
|
||
|
.set_mode = atmel_qspi_set_mode,
|
||
|
.mem_ops = &atmel_qspi_mem_ops,
|
||
|
};
|
||
|
|
||
|
static const struct atmel_qspi_caps atmel_sama5d2_qspi_caps = {};
|
||
|
|
||
|
static const struct atmel_qspi_caps atmel_sam9x60_qspi_caps = {
|
||
|
.has_qspick = true,
|
||
|
.has_ricr = true,
|
||
|
};
|
||
|
|
||
|
static const struct udevice_id atmel_qspi_ids[] = {
|
||
|
{
|
||
|
.compatible = "atmel,sama5d2-qspi",
|
||
|
.data = (ulong)&atmel_sama5d2_qspi_caps,
|
||
|
},
|
||
|
{
|
||
|
.compatible = "microchip,sam9x60-qspi",
|
||
|
.data = (ulong)&atmel_sam9x60_qspi_caps,
|
||
|
},
|
||
|
{ /* sentinel */ }
|
||
|
};
|
||
|
|
||
|
U_BOOT_DRIVER(atmel_qspi) = {
|
||
|
.name = "atmel_qspi",
|
||
|
.id = UCLASS_SPI,
|
||
|
.of_match = atmel_qspi_ids,
|
||
|
.ops = &atmel_qspi_ops,
|
||
|
.priv_auto_alloc_size = sizeof(struct atmel_qspi),
|
||
|
.probe = atmel_qspi_probe,
|
||
|
};
|