mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 04:18:51 +09:00
178 lines
3.9 KiB
C
178 lines
3.9 KiB
C
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/*
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* drivers/watchdog/orion_wdt.c
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*
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* Watchdog driver for Orion/Kirkwood processors
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*
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* Authors: Tomas Hlavacek <tmshlvck@gmail.com>
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* Sylver Bruneau <sylver.bruneau@googlemail.com>
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* Marek Behun <marek.behun@nic.cz>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <common.h>
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#include <dm.h>
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#include <wdt.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct orion_wdt_priv {
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void __iomem *reg;
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int wdt_counter_offset;
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void __iomem *rstout;
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void __iomem *rstout_mask;
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u32 timeout;
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};
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#define RSTOUT_ENABLE_BIT BIT(8)
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#define RSTOUT_MASK_BIT BIT(10)
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#define WDT_ENABLE_BIT BIT(8)
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#define TIMER_CTRL 0x0000
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#define TIMER_A370_STATUS 0x04
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#define WDT_AXP_FIXED_ENABLE_BIT BIT(10)
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#define WDT_A370_EXPIRED BIT(31)
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static int orion_wdt_reset(struct udevice *dev)
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{
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struct orion_wdt_priv *priv = dev_get_priv(dev);
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/* Reload watchdog duration */
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writel(priv->timeout, priv->reg + priv->wdt_counter_offset);
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return 0;
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}
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static int orion_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
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{
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struct orion_wdt_priv *priv = dev_get_priv(dev);
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u32 reg;
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priv->timeout = (u32) timeout;
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/* Enable the fixed watchdog clock input */
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reg = readl(priv->reg + TIMER_CTRL);
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reg |= WDT_AXP_FIXED_ENABLE_BIT;
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writel(reg, priv->reg + TIMER_CTRL);
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/* Set watchdog duration */
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writel(priv->timeout, priv->reg + priv->wdt_counter_offset);
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/* Clear the watchdog expiration bit */
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reg = readl(priv->reg + TIMER_A370_STATUS);
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reg &= ~WDT_A370_EXPIRED;
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writel(reg, priv->reg + TIMER_A370_STATUS);
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/* Enable watchdog timer */
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reg = readl(priv->reg + TIMER_CTRL);
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reg |= WDT_ENABLE_BIT;
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writel(reg, priv->reg + TIMER_CTRL);
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/* Enable reset on watchdog */
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reg = readl(priv->rstout);
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reg |= RSTOUT_ENABLE_BIT;
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writel(reg, priv->rstout);
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reg = readl(priv->rstout_mask);
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reg &= ~RSTOUT_MASK_BIT;
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writel(reg, priv->rstout_mask);
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return 0;
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}
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static int orion_wdt_stop(struct udevice *dev)
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{
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struct orion_wdt_priv *priv = dev_get_priv(dev);
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u32 reg;
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/* Disable reset on watchdog */
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reg = readl(priv->rstout_mask);
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reg |= RSTOUT_MASK_BIT;
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writel(reg, priv->rstout_mask);
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reg = readl(priv->rstout);
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reg &= ~RSTOUT_ENABLE_BIT;
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writel(reg, priv->rstout);
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/* Disable watchdog timer */
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reg = readl(priv->reg + TIMER_CTRL);
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reg &= ~WDT_ENABLE_BIT;
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writel(reg, priv->reg + TIMER_CTRL);
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return 0;
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}
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static inline bool save_reg_from_ofdata(struct udevice *dev, int index,
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void __iomem **reg, int *offset)
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{
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fdt_addr_t addr;
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fdt_size_t off;
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addr = fdtdec_get_addr_size_auto_noparent(
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gd->fdt_blob, dev_of_offset(dev), "reg", index, &off, true);
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if (addr == FDT_ADDR_T_NONE)
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return false;
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*reg = (void __iomem *) addr;
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if (offset)
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*offset = off;
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return true;
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}
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static int orion_wdt_ofdata_to_platdata(struct udevice *dev)
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{
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struct orion_wdt_priv *priv = dev_get_priv(dev);
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if (!save_reg_from_ofdata(dev, 0, &priv->reg,
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&priv->wdt_counter_offset))
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goto err;
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if (!save_reg_from_ofdata(dev, 1, &priv->rstout, NULL))
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goto err;
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if (!save_reg_from_ofdata(dev, 2, &priv->rstout_mask, NULL))
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goto err;
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return 0;
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err:
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debug("%s: Could not determine Orion wdt IO addresses\n", __func__);
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return -ENXIO;
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}
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static int orion_wdt_probe(struct udevice *dev)
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{
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debug("%s: Probing wdt%u\n", __func__, dev->seq);
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orion_wdt_stop(dev);
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return 0;
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}
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static const struct wdt_ops orion_wdt_ops = {
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.start = orion_wdt_start,
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.reset = orion_wdt_reset,
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.stop = orion_wdt_stop,
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};
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static const struct udevice_id orion_wdt_ids[] = {
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{ .compatible = "marvell,armada-380-wdt" },
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{}
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};
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U_BOOT_DRIVER(orion_wdt) = {
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.name = "orion_wdt",
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.id = UCLASS_WDT,
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.of_match = orion_wdt_ids,
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.probe = orion_wdt_probe,
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.priv_auto_alloc_size = sizeof(struct orion_wdt_priv),
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.ofdata_to_platdata = orion_wdt_ofdata_to_platdata,
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.ops = &orion_wdt_ops,
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};
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