2006-11-04 10:33:44 +09:00
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/*
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* Copyright (C) 2006 Freescale Semiconductor, Inc.
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*
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* Dave Liu <daveliu@freescale.com>
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* based on board/mpc8349emds/mpc8349emds.c
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <i2c.h>
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#include <spd.h>
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#include <miiphy.h>
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#include <command.h>
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#if defined(CONFIG_PCI)
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#include <pci.h>
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#endif
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#if defined(CONFIG_SPD_EEPROM)
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#include <spd_sdram.h>
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#else
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#include <asm/mmu.h>
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#endif
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2006-11-01 15:10:40 +09:00
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#if defined(CONFIG_OF_FLAT_TREE)
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#include <ft_build.h>
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#endif
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2007-04-01 01:23:51 +09:00
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#if defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#include <libfdt_env.h>
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#endif
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2006-11-04 10:33:44 +09:00
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2006-11-04 03:11:15 +09:00
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* GETH1 */
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{0, 3, 1, 0, 1}, /* TxD0 */
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{0, 4, 1, 0, 1}, /* TxD1 */
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{0, 5, 1, 0, 1}, /* TxD2 */
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{0, 6, 1, 0, 1}, /* TxD3 */
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{1, 6, 1, 0, 3}, /* TxD4 */
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{1, 7, 1, 0, 1}, /* TxD5 */
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{1, 9, 1, 0, 2}, /* TxD6 */
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{1, 10, 1, 0, 2}, /* TxD7 */
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{0, 9, 2, 0, 1}, /* RxD0 */
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{0, 10, 2, 0, 1}, /* RxD1 */
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{0, 11, 2, 0, 1}, /* RxD2 */
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{0, 12, 2, 0, 1}, /* RxD3 */
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{0, 13, 2, 0, 1}, /* RxD4 */
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{1, 1, 2, 0, 2}, /* RxD5 */
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{1, 0, 2, 0, 2}, /* RxD6 */
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{1, 4, 2, 0, 2}, /* RxD7 */
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{0, 7, 1, 0, 1}, /* TX_EN */
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{0, 8, 1, 0, 1}, /* TX_ER */
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{0, 15, 2, 0, 1}, /* RX_DV */
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{0, 16, 2, 0, 1}, /* RX_ER */
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{0, 0, 2, 0, 1}, /* RX_CLK */
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{2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
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{2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
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/* GETH2 */
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{0, 17, 1, 0, 1}, /* TxD0 */
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{0, 18, 1, 0, 1}, /* TxD1 */
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{0, 19, 1, 0, 1}, /* TxD2 */
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{0, 20, 1, 0, 1}, /* TxD3 */
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{1, 2, 1, 0, 1}, /* TxD4 */
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{1, 3, 1, 0, 2}, /* TxD5 */
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{1, 5, 1, 0, 3}, /* TxD6 */
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{1, 8, 1, 0, 3}, /* TxD7 */
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{0, 23, 2, 0, 1}, /* RxD0 */
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{0, 24, 2, 0, 1}, /* RxD1 */
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{0, 25, 2, 0, 1}, /* RxD2 */
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{0, 26, 2, 0, 1}, /* RxD3 */
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{0, 27, 2, 0, 1}, /* RxD4 */
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{1, 12, 2, 0, 2}, /* RxD5 */
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{1, 13, 2, 0, 3}, /* RxD6 */
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{1, 11, 2, 0, 2}, /* RxD7 */
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{0, 21, 1, 0, 1}, /* TX_EN */
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{0, 22, 1, 0, 1}, /* TX_ER */
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{0, 29, 2, 0, 1}, /* RX_DV */
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{0, 30, 2, 0, 1}, /* RX_ER */
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{0, 31, 2, 0, 1}, /* RX_CLK */
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{2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
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{2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
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{0, 1, 3, 0, 2}, /* MDIO */
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{0, 2, 1, 0, 1}, /* MDC */
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
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};
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2006-11-04 10:33:44 +09:00
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int board_early_init_f(void)
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{
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2007-02-15 10:50:53 +09:00
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u8 *bcsr = (u8 *)CFG_BCSR;
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const immap_t *immr = (immap_t *)CFG_IMMR;
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2006-11-04 10:33:44 +09:00
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/* Enable flash write */
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bcsr[0xa] &= ~0x04;
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2007-02-15 10:50:53 +09:00
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/* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2 h/w bug workaround) */
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if (immr->sysconf.spridr == SPR_8360_REV20 ||
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immr->sysconf.spridr == SPR_8360E_REV20)
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bcsr[0xe] = 0x30;
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2006-11-04 10:33:44 +09:00
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return 0;
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}
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
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extern void ddr_enable_ecc(unsigned int dram_size);
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#endif
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int fixed_sdram(void);
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void sdram_init(void);
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long int initdram(int board_type)
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{
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2006-11-04 03:00:28 +09:00
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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2006-11-04 10:33:44 +09:00
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
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#if defined(CONFIG_SPD_EEPROM)
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msize = spd_sdram();
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#else
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msize = fixed_sdram();
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#endif
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#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
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/*
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* Initialize DDR ECC byte
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*/
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ddr_enable_ecc(msize * 1024 * 1024);
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#endif
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/*
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* Initialize SDRAM if it is on local bus.
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*/
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sdram_init();
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puts(" DDR RAM: ");
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/* return total bus SDRAM size(bytes) -- DDR */
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return (msize * 1024 * 1024);
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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2006-11-04 03:00:28 +09:00
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volatile immap_t *im = (immap_t *) CFG_IMMR;
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2006-11-04 10:33:44 +09:00
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CFG_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
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if (ddr_size & 1) {
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return -1;
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}
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}
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im->sysconf.ddrlaw[0].ar =
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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#if (CFG_DDR_SIZE != 256)
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#warning Currenly any ddr size other than 256 is not supported
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#endif
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2007-02-14 19:27:17 +09:00
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#ifdef CONFIG_DDR_II
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im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
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im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
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im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CFG_DDR_MODE;
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im->ddr.sdram_mode2 = CFG_DDR_MODE2;
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im->ddr.sdram_interval = CFG_DDR_INTERVAL;
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im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
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#else
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2006-11-04 10:33:44 +09:00
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im->ddr.csbnds[0].csbnds = 0x00000007;
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im->ddr.csbnds[1].csbnds = 0x0008000f;
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im->ddr.cs_config[0] = CFG_DDR_CONFIG;
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im->ddr.cs_config[1] = CFG_DDR_CONFIG;
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im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
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im->ddr.sdram_cfg = CFG_DDR_CONTROL;
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im->ddr.sdram_mode = CFG_DDR_MODE;
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im->ddr.sdram_interval = CFG_DDR_INTERVAL;
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2007-02-14 19:27:17 +09:00
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#endif
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2006-11-04 10:33:44 +09:00
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udelay(200);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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return msize;
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}
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#endif /*!CFG_SPD_EEPROM */
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int checkboard(void)
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{
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puts("Board: Freescale MPC8360EMDS\n");
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return 0;
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}
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/*
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* if MPC8360EMDS is soldered with SDRAM
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*/
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#if defined(CFG_BR2_PRELIM) \
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&& defined(CFG_OR2_PRELIM) \
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&& defined(CFG_LBLAWBAR2_PRELIM) \
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&& defined(CFG_LBLAWAR2_PRELIM)
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/*
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* Initialize SDRAM memory on the Local Bus.
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*/
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void sdram_init(void)
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{
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2006-11-04 03:00:28 +09:00
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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2006-11-04 10:33:44 +09:00
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volatile lbus83xx_t *lbc = &immap->lbus;
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uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
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puts("\n SDRAM on Local Bus: ");
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print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
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/*
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* Setup SDRAM Base and Option Registers, already done in cpu_init.c
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*/
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/*setup mtrpt, lsrt and lbcr for LB bus */
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lbc->lbcr = CFG_LBC_LBCR;
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lbc->mrtpr = CFG_LBC_MRTPR;
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lbc->lsrt = CFG_LBC_LSRT;
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asm("sync");
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/*
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* Configure the SDRAM controller Machine Mode Register.
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*/
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lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */
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lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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/*
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* We need do 8 times auto refresh operation.
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*/
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lbc->lsdmr = CFG_LBC_LSDMR_2;
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asm("sync");
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*sdram_addr = 0xff; /* 1 times */
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udelay(100);
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*sdram_addr = 0xff; /* 2 times */
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udelay(100);
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*sdram_addr = 0xff; /* 3 times */
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udelay(100);
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*sdram_addr = 0xff; /* 4 times */
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udelay(100);
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*sdram_addr = 0xff; /* 5 times */
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udelay(100);
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*sdram_addr = 0xff; /* 6 times */
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udelay(100);
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*sdram_addr = 0xff; /* 7 times */
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udelay(100);
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*sdram_addr = 0xff; /* 8 times */
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udelay(100);
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/* Mode register write operation */
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lbc->lsdmr = CFG_LBC_LSDMR_4;
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asm("sync");
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*(sdram_addr + 0xcc) = 0xff;
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udelay(100);
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/* Normal operation */
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lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
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asm("sync");
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*sdram_addr = 0xff;
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udelay(100);
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}
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#else
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void sdram_init(void)
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{
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puts("SDRAM on Local Bus is NOT available!\n");
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}
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#endif
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#if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD)
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/*
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* ECC user commands
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*/
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void ecc_print_status(void)
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{
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2006-11-04 03:00:28 +09:00
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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2006-11-04 10:33:44 +09:00
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volatile ddr83xx_t *ddr = &immap->ddr;
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printf("\nECC mode: %s\n\n",
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(ddr->sdram_cfg & SDRAM_CFG_ECC_EN) ? "ON" : "OFF");
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/* Interrupts */
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printf("Memory Error Interrupt Enable:\n");
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printf(" Multiple-Bit Error Interrupt Enable: %d\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_MBEE) ? 1 : 0);
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printf(" Single-Bit Error Interrupt Enable: %d\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_SBEE) ? 1 : 0);
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printf(" Memory Select Error Interrupt Enable: %d\n\n",
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(ddr->err_int_en & ECC_ERR_INT_EN_MSEE) ? 1 : 0);
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/* Error disable */
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printf("Memory Error Disable:\n");
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printf(" Multiple-Bit Error Disable: %d\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_MBED) ? 1 : 0);
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printf(" Sinle-Bit Error Disable: %d\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_SBED) ? 1 : 0);
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printf(" Memory Select Error Disable: %d\n\n",
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(ddr->err_disable & ECC_ERROR_DISABLE_MSED) ? 1 : 0);
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/* Error injection */
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|
|
printf("Memory Data Path Error Injection Mask High/Low: %08lx %08lx\n",
|
|
|
|
ddr->data_err_inject_hi, ddr->data_err_inject_lo);
|
|
|
|
|
|
|
|
printf("Memory Data Path Error Injection Mask ECC:\n");
|
|
|
|
printf(" ECC Mirror Byte: %d\n",
|
|
|
|
(ddr->ecc_err_inject & ECC_ERR_INJECT_EMB) ? 1 : 0);
|
|
|
|
printf(" ECC Injection Enable: %d\n",
|
|
|
|
(ddr->ecc_err_inject & ECC_ERR_INJECT_EIEN) ? 1 : 0);
|
|
|
|
printf(" ECC Error Injection Mask: 0x%02x\n\n",
|
|
|
|
ddr->ecc_err_inject & ECC_ERR_INJECT_EEIM);
|
|
|
|
|
|
|
|
/* SBE counter/threshold */
|
|
|
|
printf("Memory Single-Bit Error Management (0..255):\n");
|
|
|
|
printf(" Single-Bit Error Threshold: %d\n",
|
|
|
|
(ddr->err_sbe & ECC_ERROR_MAN_SBET) >> ECC_ERROR_MAN_SBET_SHIFT);
|
|
|
|
printf(" Single-Bit Error Counter: %d\n\n",
|
|
|
|
(ddr->err_sbe & ECC_ERROR_MAN_SBEC) >> ECC_ERROR_MAN_SBEC_SHIFT);
|
|
|
|
|
|
|
|
/* Error detect */
|
|
|
|
printf("Memory Error Detect:\n");
|
|
|
|
printf(" Multiple Memory Errors: %d\n",
|
|
|
|
(ddr->err_detect & ECC_ERROR_DETECT_MME) ? 1 : 0);
|
|
|
|
printf(" Multiple-Bit Error: %d\n",
|
|
|
|
(ddr->err_detect & ECC_ERROR_DETECT_MBE) ? 1 : 0);
|
|
|
|
printf(" Single-Bit Error: %d\n",
|
|
|
|
(ddr->err_detect & ECC_ERROR_DETECT_SBE) ? 1 : 0);
|
|
|
|
printf(" Memory Select Error: %d\n\n",
|
|
|
|
(ddr->err_detect & ECC_ERROR_DETECT_MSE) ? 1 : 0);
|
|
|
|
|
|
|
|
/* Capture data */
|
|
|
|
printf("Memory Error Address Capture: 0x%08lx\n", ddr->capture_address);
|
|
|
|
printf("Memory Data Path Read Capture High/Low: %08lx %08lx\n",
|
|
|
|
ddr->capture_data_hi, ddr->capture_data_lo);
|
|
|
|
printf("Memory Data Path Read Capture ECC: 0x%02x\n\n",
|
|
|
|
ddr->capture_ecc & CAPTURE_ECC_ECE);
|
|
|
|
|
|
|
|
printf("Memory Error Attributes Capture:\n");
|
|
|
|
printf(" Data Beat Number: %d\n",
|
|
|
|
(ddr->capture_attributes & ECC_CAPT_ATTR_BNUM) >>
|
|
|
|
ECC_CAPT_ATTR_BNUM_SHIFT);
|
|
|
|
printf(" Transaction Size: %d\n",
|
|
|
|
(ddr->capture_attributes & ECC_CAPT_ATTR_TSIZ) >>
|
|
|
|
ECC_CAPT_ATTR_TSIZ_SHIFT);
|
|
|
|
printf(" Transaction Source: %d\n",
|
|
|
|
(ddr->capture_attributes & ECC_CAPT_ATTR_TSRC) >>
|
|
|
|
ECC_CAPT_ATTR_TSRC_SHIFT);
|
|
|
|
printf(" Transaction Type: %d\n",
|
|
|
|
(ddr->capture_attributes & ECC_CAPT_ATTR_TTYP) >>
|
|
|
|
ECC_CAPT_ATTR_TTYP_SHIFT);
|
|
|
|
printf(" Error Information Valid: %d\n\n",
|
|
|
|
ddr->capture_attributes & ECC_CAPT_ATTR_VLD);
|
|
|
|
}
|
|
|
|
|
|
|
|
int do_ecc(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
|
|
|
|
{
|
2006-11-04 03:00:28 +09:00
|
|
|
volatile immap_t *immap = (immap_t *) CFG_IMMR;
|
2006-11-04 10:33:44 +09:00
|
|
|
volatile ddr83xx_t *ddr = &immap->ddr;
|
|
|
|
volatile u32 val;
|
|
|
|
u64 *addr;
|
|
|
|
u32 count;
|
|
|
|
register u64 *i;
|
|
|
|
u32 ret[2];
|
|
|
|
u32 pattern[2];
|
|
|
|
u32 writeback[2];
|
|
|
|
|
|
|
|
/* The pattern is written into memory to generate error */
|
|
|
|
pattern[0] = 0xfedcba98UL;
|
|
|
|
pattern[1] = 0x76543210UL;
|
|
|
|
|
|
|
|
/* After injecting error, re-initialize the memory with the value */
|
|
|
|
writeback[0] = 0x01234567UL;
|
|
|
|
writeback[1] = 0x89abcdefUL;
|
|
|
|
|
|
|
|
if (argc > 4) {
|
|
|
|
printf("Usage:\n%s\n", cmdtp->usage);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (argc == 2) {
|
|
|
|
if (strcmp(argv[1], "status") == 0) {
|
|
|
|
ecc_print_status();
|
|
|
|
return 0;
|
|
|
|
} else if (strcmp(argv[1], "captureclear") == 0) {
|
|
|
|
ddr->capture_address = 0;
|
|
|
|
ddr->capture_data_hi = 0;
|
|
|
|
ddr->capture_data_lo = 0;
|
|
|
|
ddr->capture_ecc = 0;
|
|
|
|
ddr->capture_attributes = 0;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (argc == 3) {
|
|
|
|
if (strcmp(argv[1], "sbecnt") == 0) {
|
|
|
|
val = simple_strtoul(argv[2], NULL, 10);
|
|
|
|
if (val > 255) {
|
|
|
|
printf("Incorrect Counter value, "
|
|
|
|
"should be 0..255\n");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
val = (val << ECC_ERROR_MAN_SBEC_SHIFT);
|
|
|
|
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBET);
|
|
|
|
|
|
|
|
ddr->err_sbe = val;
|
|
|
|
return 0;
|
|
|
|
} else if (strcmp(argv[1], "sbethr") == 0) {
|
|
|
|
val = simple_strtoul(argv[2], NULL, 10);
|
|
|
|
if (val > 255) {
|
|
|
|
printf("Incorrect Counter value, "
|
|
|
|
"should be 0..255\n");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
val = (val << ECC_ERROR_MAN_SBET_SHIFT);
|
|
|
|
val |= (ddr->err_sbe & ECC_ERROR_MAN_SBEC);
|
|
|
|
|
|
|
|
ddr->err_sbe = val;
|
|
|
|
return 0;
|
|
|
|
} else if (strcmp(argv[1], "errdisable") == 0) {
|
|
|
|
val = ddr->err_disable;
|
|
|
|
|
|
|
|
if (strcmp(argv[2], "+sbe") == 0) {
|
|
|
|
val |= ECC_ERROR_DISABLE_SBED;
|
|
|
|
} else if (strcmp(argv[2], "+mbe") == 0) {
|
|
|
|
val |= ECC_ERROR_DISABLE_MBED;
|
|
|
|
} else if (strcmp(argv[2], "+mse") == 0) {
|
|
|
|
val |= ECC_ERROR_DISABLE_MSED;
|
|
|
|
} else if (strcmp(argv[2], "+all") == 0) {
|
|
|
|
val |= (ECC_ERROR_DISABLE_SBED |
|
|
|
|
ECC_ERROR_DISABLE_MBED |
|
|
|
|
ECC_ERROR_DISABLE_MSED);
|
|
|
|
} else if (strcmp(argv[2], "-sbe") == 0) {
|
|
|
|
val &= ~ECC_ERROR_DISABLE_SBED;
|
|
|
|
} else if (strcmp(argv[2], "-mbe") == 0) {
|
|
|
|
val &= ~ECC_ERROR_DISABLE_MBED;
|
|
|
|
} else if (strcmp(argv[2], "-mse") == 0) {
|
|
|
|
val &= ~ECC_ERROR_DISABLE_MSED;
|
|
|
|
} else if (strcmp(argv[2], "-all") == 0) {
|
|
|
|
val &= ~(ECC_ERROR_DISABLE_SBED |
|
|
|
|
ECC_ERROR_DISABLE_MBED |
|
|
|
|
ECC_ERROR_DISABLE_MSED);
|
|
|
|
} else {
|
|
|
|
printf("Incorrect err_disable field\n");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
ddr->err_disable = val;
|
|
|
|
__asm__ __volatile__("sync");
|
|
|
|
__asm__ __volatile__("isync");
|
|
|
|
return 0;
|
|
|
|
} else if (strcmp(argv[1], "errdetectclr") == 0) {
|
|
|
|
val = ddr->err_detect;
|
|
|
|
|
|
|
|
if (strcmp(argv[2], "mme") == 0) {
|
|
|
|
val |= ECC_ERROR_DETECT_MME;
|
|
|
|
} else if (strcmp(argv[2], "sbe") == 0) {
|
|
|
|
val |= ECC_ERROR_DETECT_SBE;
|
|
|
|
} else if (strcmp(argv[2], "mbe") == 0) {
|
|
|
|
val |= ECC_ERROR_DETECT_MBE;
|
|
|
|
} else if (strcmp(argv[2], "mse") == 0) {
|
|
|
|
val |= ECC_ERROR_DETECT_MSE;
|
|
|
|
} else if (strcmp(argv[2], "all") == 0) {
|
|
|
|
val |= (ECC_ERROR_DETECT_MME |
|
|
|
|
ECC_ERROR_DETECT_MBE |
|
|
|
|
ECC_ERROR_DETECT_SBE |
|
|
|
|
ECC_ERROR_DETECT_MSE);
|
|
|
|
} else {
|
|
|
|
printf("Incorrect err_detect field\n");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
ddr->err_detect = val;
|
|
|
|
return 0;
|
|
|
|
} else if (strcmp(argv[1], "injectdatahi") == 0) {
|
|
|
|
val = simple_strtoul(argv[2], NULL, 16);
|
|
|
|
|
|
|
|
ddr->data_err_inject_hi = val;
|
|
|
|
return 0;
|
|
|
|
} else if (strcmp(argv[1], "injectdatalo") == 0) {
|
|
|
|
val = simple_strtoul(argv[2], NULL, 16);
|
|
|
|
|
|
|
|
ddr->data_err_inject_lo = val;
|
|
|
|
return 0;
|
|
|
|
} else if (strcmp(argv[1], "injectecc") == 0) {
|
|
|
|
val = simple_strtoul(argv[2], NULL, 16);
|
|
|
|
if (val > 0xff) {
|
|
|
|
printf("Incorrect ECC inject mask, "
|
|
|
|
"should be 0x00..0xff\n");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
val |= (ddr->ecc_err_inject & ~ECC_ERR_INJECT_EEIM);
|
|
|
|
|
|
|
|
ddr->ecc_err_inject = val;
|
|
|
|
return 0;
|
|
|
|
} else if (strcmp(argv[1], "inject") == 0) {
|
|
|
|
val = ddr->ecc_err_inject;
|
|
|
|
|
|
|
|
if (strcmp(argv[2], "en") == 0)
|
|
|
|
val |= ECC_ERR_INJECT_EIEN;
|
|
|
|
else if (strcmp(argv[2], "dis") == 0)
|
|
|
|
val &= ~ECC_ERR_INJECT_EIEN;
|
|
|
|
else
|
|
|
|
printf("Incorrect command\n");
|
|
|
|
|
|
|
|
ddr->ecc_err_inject = val;
|
|
|
|
__asm__ __volatile__("sync");
|
|
|
|
__asm__ __volatile__("isync");
|
|
|
|
return 0;
|
|
|
|
} else if (strcmp(argv[1], "mirror") == 0) {
|
|
|
|
val = ddr->ecc_err_inject;
|
|
|
|
|
|
|
|
if (strcmp(argv[2], "en") == 0)
|
|
|
|
val |= ECC_ERR_INJECT_EMB;
|
|
|
|
else if (strcmp(argv[2], "dis") == 0)
|
|
|
|
val &= ~ECC_ERR_INJECT_EMB;
|
|
|
|
else
|
|
|
|
printf("Incorrect command\n");
|
|
|
|
|
|
|
|
ddr->ecc_err_inject = val;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (argc == 4) {
|
|
|
|
if (strcmp(argv[1], "testdw") == 0) {
|
|
|
|
addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
|
|
|
|
count = simple_strtoul(argv[3], NULL, 16);
|
|
|
|
|
|
|
|
if ((u32) addr % 8) {
|
|
|
|
printf("Address not alligned on "
|
|
|
|
"double word boundary\n");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
disable_interrupts();
|
|
|
|
|
|
|
|
for (i = addr; i < addr + count; i++) {
|
|
|
|
|
|
|
|
/* enable injects */
|
|
|
|
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
|
|
|
|
__asm__ __volatile__("sync");
|
|
|
|
__asm__ __volatile__("isync");
|
|
|
|
|
|
|
|
/* write memory location injecting errors */
|
|
|
|
ppcDWstore((u32 *) i, pattern);
|
mpc83xx: Fix the incorrect dcbz operation
The 834x rev1.x silicon has one CPU5 errata.
The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.
The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.
The 834x rev3.0 and later and 8360 have not this bug inside.
So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.
However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.
This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.
CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.
Signed-off-by: Dave Liu <daveliu@freescale.com>
2006-11-03 09:05:50 +09:00
|
|
|
__asm__ __volatile__("sync");
|
2006-11-04 10:33:44 +09:00
|
|
|
|
|
|
|
/* disable injects */
|
|
|
|
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
|
|
|
|
__asm__ __volatile__("sync");
|
|
|
|
__asm__ __volatile__("isync");
|
|
|
|
|
|
|
|
/* read data, this generates ECC error */
|
|
|
|
ppcDWload((u32 *) i, ret);
|
mpc83xx: Fix the incorrect dcbz operation
The 834x rev1.x silicon has one CPU5 errata.
The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.
The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.
The 834x rev3.0 and later and 8360 have not this bug inside.
So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.
However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.
This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.
CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.
Signed-off-by: Dave Liu <daveliu@freescale.com>
2006-11-03 09:05:50 +09:00
|
|
|
__asm__ __volatile__("sync");
|
2006-11-04 10:33:44 +09:00
|
|
|
|
|
|
|
/* re-initialize memory, double word write the location again,
|
|
|
|
* generates new ECC code this time */
|
|
|
|
ppcDWstore((u32 *) i, writeback);
|
mpc83xx: Fix the incorrect dcbz operation
The 834x rev1.x silicon has one CPU5 errata.
The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.
The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.
The 834x rev3.0 and later and 8360 have not this bug inside.
So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.
However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.
This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.
CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.
Signed-off-by: Dave Liu <daveliu@freescale.com>
2006-11-03 09:05:50 +09:00
|
|
|
__asm__ __volatile__("sync");
|
2006-11-04 10:33:44 +09:00
|
|
|
}
|
|
|
|
enable_interrupts();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
if (strcmp(argv[1], "testword") == 0) {
|
|
|
|
addr = (u64 *) simple_strtoul(argv[2], NULL, 16);
|
|
|
|
count = simple_strtoul(argv[3], NULL, 16);
|
|
|
|
|
|
|
|
if ((u32) addr % 8) {
|
|
|
|
printf("Address not alligned on "
|
|
|
|
"double word boundary\n");
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
disable_interrupts();
|
|
|
|
|
|
|
|
for (i = addr; i < addr + count; i++) {
|
|
|
|
|
|
|
|
/* enable injects */
|
|
|
|
ddr->ecc_err_inject |= ECC_ERR_INJECT_EIEN;
|
|
|
|
__asm__ __volatile__("sync");
|
|
|
|
__asm__ __volatile__("isync");
|
|
|
|
|
|
|
|
/* write memory location injecting errors */
|
|
|
|
*(u32 *) i = 0xfedcba98UL;
|
|
|
|
__asm__ __volatile__("sync");
|
|
|
|
|
|
|
|
/* sub double word write,
|
|
|
|
* bus will read-modify-write,
|
|
|
|
* generates ECC error */
|
|
|
|
*((u32 *) i + 1) = 0x76543210UL;
|
|
|
|
__asm__ __volatile__("sync");
|
|
|
|
|
|
|
|
/* disable injects */
|
|
|
|
ddr->ecc_err_inject &= ~ECC_ERR_INJECT_EIEN;
|
|
|
|
__asm__ __volatile__("sync");
|
|
|
|
__asm__ __volatile__("isync");
|
|
|
|
|
|
|
|
/* re-initialize memory,
|
|
|
|
* double word write the location again,
|
|
|
|
* generates new ECC code this time */
|
|
|
|
ppcDWstore((u32 *) i, writeback);
|
mpc83xx: Fix the incorrect dcbz operation
The 834x rev1.x silicon has one CPU5 errata.
The issue is when the data cache locked with
HID0[DLOCK], the dcbz instruction looks like no-op inst.
The right behavior of the data cache is when the data cache
Locked with HID0[DLOCK], the dcbz instruction allocates
new tags in cache.
The 834x rev3.0 and later and 8360 have not this bug inside.
So, when 834x rev3.0/8360 are working with ECC, the dcbz
instruction will corrupt the stack in cache, the processor will
checkstop reset.
However, the 834x rev1.x can work with ECC with these code,
because the sillicon has this cache bug. The dcbz will not
corrupt the stack in cache.
Really, it is the fault code running on fault sillicon.
This patch fix the incorrect dcbz operation. Instead of
CPU FP writing to initialise the ECC.
CHANGELOG:
* Fix the incorrect dcbz operation instead of CPU FP
writing to initialise the ECC memory. Otherwise, it
will corrupt the stack in cache, The processor will checkstop
reset.
Signed-off-by: Dave Liu <daveliu@freescale.com>
2006-11-03 09:05:50 +09:00
|
|
|
__asm__ __volatile__("sync");
|
2006-11-04 10:33:44 +09:00
|
|
|
}
|
|
|
|
enable_interrupts();
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
printf("Usage:\n%s\n", cmdtp->usage);
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
U_BOOT_CMD(ecc, 4, 0, do_ecc,
|
|
|
|
"ecc - support for DDR ECC features\n",
|
|
|
|
"status - print out status info\n"
|
|
|
|
"ecc captureclear - clear capture regs data\n"
|
|
|
|
"ecc sbecnt <val> - set Single-Bit Error counter\n"
|
|
|
|
"ecc sbethr <val> - set Single-Bit Threshold\n"
|
|
|
|
"ecc errdisable <flag> - clear/set disable Memory Error Disable, flag:\n"
|
|
|
|
" [-|+]sbe - Single-Bit Error\n"
|
|
|
|
" [-|+]mbe - Multiple-Bit Error\n"
|
|
|
|
" [-|+]mse - Memory Select Error\n"
|
|
|
|
" [-|+]all - all errors\n"
|
|
|
|
"ecc errdetectclr <flag> - clear Memory Error Detect, flag:\n"
|
|
|
|
" mme - Multiple Memory Errors\n"
|
|
|
|
" sbe - Single-Bit Error\n"
|
|
|
|
" mbe - Multiple-Bit Error\n"
|
|
|
|
" mse - Memory Select Error\n"
|
|
|
|
" all - all errors\n"
|
|
|
|
"ecc injectdatahi <hi> - set Memory Data Path Error Injection Mask High\n"
|
|
|
|
"ecc injectdatalo <lo> - set Memory Data Path Error Injection Mask Low\n"
|
|
|
|
"ecc injectecc <ecc> - set ECC Error Injection Mask\n"
|
|
|
|
"ecc inject <en|dis> - enable/disable error injection\n"
|
|
|
|
"ecc mirror <en|dis> - enable/disable mirror byte\n"
|
|
|
|
"ecc testdw <addr> <cnt> - test mem region with double word access:\n"
|
|
|
|
" - enables injects\n"
|
|
|
|
" - writes pattern injecting errors with double word access\n"
|
|
|
|
" - disables injects\n"
|
|
|
|
" - reads pattern back with double word access, generates error\n"
|
|
|
|
" - re-inits memory\n"
|
|
|
|
"ecc testword <addr> <cnt> - test mem region with word access:\n"
|
|
|
|
" - enables injects\n"
|
|
|
|
" - writes pattern injecting errors with word access\n"
|
|
|
|
" - writes pattern with word access, generates error\n"
|
|
|
|
" - disables injects\n" " - re-inits memory");
|
|
|
|
#endif /* if defined(CONFIG_DDR_ECC) && defined(CONFIG_DDR_ECC_CMD) */
|
2006-11-01 15:10:40 +09:00
|
|
|
|
2007-04-01 01:23:51 +09:00
|
|
|
#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
|
|
|
|
&& defined(CONFIG_OF_BOARD_SETUP)
|
2007-04-07 03:19:43 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Prototypes of functions that we use.
|
|
|
|
*/
|
|
|
|
void ft_cpu_setup(void *blob, bd_t *bd);
|
|
|
|
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
void ft_pci_setup(void *blob, bd_t *bd);
|
|
|
|
#endif
|
|
|
|
|
2006-11-01 15:10:40 +09:00
|
|
|
void
|
|
|
|
ft_board_setup(void *blob, bd_t *bd)
|
|
|
|
{
|
2007-04-01 01:23:51 +09:00
|
|
|
#if defined(CONFIG_OF_LIBFDT)
|
|
|
|
int nodeoffset;
|
|
|
|
int tmp[2];
|
|
|
|
|
|
|
|
nodeoffset = fdt_path_offset (fdt, "/memory");
|
|
|
|
if (nodeoffset >= 0) {
|
|
|
|
tmp[0] = cpu_to_be32(bd->bi_memstart);
|
|
|
|
tmp[1] = cpu_to_be32(bd->bi_memsize);
|
2007-04-07 03:19:43 +09:00
|
|
|
fdt_setprop(fdt, nodeoffset, "reg", tmp, sizeof(tmp));
|
2007-04-01 01:23:51 +09:00
|
|
|
}
|
|
|
|
#else
|
2006-11-01 15:10:40 +09:00
|
|
|
u32 *p;
|
|
|
|
int len;
|
|
|
|
|
|
|
|
p = ft_get_prop(blob, "/memory/reg", &len);
|
|
|
|
if (p != NULL) {
|
|
|
|
*p++ = cpu_to_be32(bd->bi_memstart);
|
|
|
|
*p = cpu_to_be32(bd->bi_memsize);
|
|
|
|
}
|
2007-04-01 01:23:51 +09:00
|
|
|
#endif
|
|
|
|
|
|
|
|
#ifdef CONFIG_PCI
|
|
|
|
ft_pci_setup(blob, bd);
|
|
|
|
#endif
|
|
|
|
ft_cpu_setup(blob, bd);
|
2006-11-01 15:10:40 +09:00
|
|
|
}
|
2007-04-07 03:19:43 +09:00
|
|
|
#endif /* CONFIG_OF_x */
|