mirror of
https://github.com/brain-hackers/u-boot-brain
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179 lines
3.9 KiB
C
179 lines
3.9 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2017-2018 Vasily Khoruzhick <anarsoul@gmail.com>
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*/
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#include <common.h>
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#include <div64.h>
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#include <dm.h>
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#include <pwm.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/arch/pwm.h>
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#include <asm/arch/gpio.h>
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#include <power/regulator.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define OSC_24MHZ 24000000
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struct sunxi_pwm_priv {
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struct sunxi_pwm *regs;
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bool invert;
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u32 prescaler;
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};
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static const u32 prescaler_table[] = {
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120, /* 0000 */
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180, /* 0001 */
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240, /* 0010 */
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360, /* 0011 */
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480, /* 0100 */
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0, /* 0101 */
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0, /* 0110 */
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0, /* 0111 */
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12000, /* 1000 */
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24000, /* 1001 */
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36000, /* 1010 */
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48000, /* 1011 */
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72000, /* 1100 */
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0, /* 1101 */
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0, /* 1110 */
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1, /* 1111 */
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};
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static int sunxi_pwm_config_pinmux(void)
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{
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#ifdef CONFIG_MACH_SUN50I
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sunxi_gpio_set_cfgpin(SUNXI_GPD(22), SUNXI_GPD_PWM);
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#endif
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return 0;
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}
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static int sunxi_pwm_set_invert(struct udevice *dev, uint channel,
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bool polarity)
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{
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struct sunxi_pwm_priv *priv = dev_get_priv(dev);
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debug("%s: polarity=%u\n", __func__, polarity);
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priv->invert = polarity;
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return 0;
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}
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static int sunxi_pwm_set_config(struct udevice *dev, uint channel,
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uint period_ns, uint duty_ns)
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{
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struct sunxi_pwm_priv *priv = dev_get_priv(dev);
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struct sunxi_pwm *regs = priv->regs;
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int prescaler;
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u32 v, period = 0, duty;
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u64 scaled_freq = 0;
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const u32 nsecs_per_sec = 1000000000U;
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debug("%s: period_ns=%u, duty_ns=%u\n", __func__, period_ns, duty_ns);
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for (prescaler = 0; prescaler < SUNXI_PWM_CTRL_PRESCALE0_MASK;
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prescaler++) {
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if (!prescaler_table[prescaler])
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continue;
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scaled_freq = lldiv(OSC_24MHZ, prescaler_table[prescaler]);
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period = lldiv(scaled_freq * period_ns, nsecs_per_sec);
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if (period - 1 <= SUNXI_PWM_CH0_PERIOD_MAX)
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break;
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}
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if (period - 1 > SUNXI_PWM_CH0_PERIOD_MAX) {
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debug("%s: failed to find prescaler value\n", __func__);
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return -EINVAL;
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}
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duty = lldiv(scaled_freq * duty_ns, nsecs_per_sec);
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if (priv->prescaler != prescaler) {
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/* Mask clock to update prescaler */
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v = readl(®s->ctrl);
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v &= ~SUNXI_PWM_CTRL_CLK_GATE;
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writel(v, ®s->ctrl);
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v &= ~SUNXI_PWM_CTRL_PRESCALE0_MASK;
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v |= (priv->prescaler & SUNXI_PWM_CTRL_PRESCALE0_MASK);
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writel(v, ®s->ctrl);
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v |= SUNXI_PWM_CTRL_CLK_GATE;
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writel(v, ®s->ctrl);
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priv->prescaler = prescaler;
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}
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writel(SUNXI_PWM_CH0_PERIOD_PRD(period) |
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SUNXI_PWM_CH0_PERIOD_DUTY(duty), ®s->ch0_period);
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debug("%s: prescaler: %d, period: %d, duty: %d\n",
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__func__, priv->prescaler,
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period, duty);
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return 0;
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}
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static int sunxi_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
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{
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struct sunxi_pwm_priv *priv = dev_get_priv(dev);
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struct sunxi_pwm *regs = priv->regs;
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u32 v;
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debug("%s: Enable '%s'\n", __func__, dev->name);
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v = readl(®s->ctrl);
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if (!enable) {
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v &= ~SUNXI_PWM_CTRL_ENABLE0;
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writel(v, ®s->ctrl);
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return 0;
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}
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sunxi_pwm_config_pinmux();
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if (priv->invert)
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v &= ~SUNXI_PWM_CTRL_CH0_ACT_STA;
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else
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v |= SUNXI_PWM_CTRL_CH0_ACT_STA;
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v |= SUNXI_PWM_CTRL_ENABLE0;
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writel(v, ®s->ctrl);
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return 0;
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}
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static int sunxi_pwm_ofdata_to_platdata(struct udevice *dev)
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{
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struct sunxi_pwm_priv *priv = dev_get_priv(dev);
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priv->regs = (struct sunxi_pwm *)devfdt_get_addr(dev);
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return 0;
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}
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static int sunxi_pwm_probe(struct udevice *dev)
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{
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return 0;
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}
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static const struct pwm_ops sunxi_pwm_ops = {
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.set_invert = sunxi_pwm_set_invert,
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.set_config = sunxi_pwm_set_config,
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.set_enable = sunxi_pwm_set_enable,
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};
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static const struct udevice_id sunxi_pwm_ids[] = {
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{ .compatible = "allwinner,sun5i-a13-pwm" },
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{ .compatible = "allwinner,sun50i-a64-pwm" },
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{ }
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};
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U_BOOT_DRIVER(sunxi_pwm) = {
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.name = "sunxi_pwm",
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.id = UCLASS_PWM,
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.of_match = sunxi_pwm_ids,
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.ops = &sunxi_pwm_ops,
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.ofdata_to_platdata = sunxi_pwm_ofdata_to_platdata,
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.probe = sunxi_pwm_probe,
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.priv_auto_alloc_size = sizeof(struct sunxi_pwm_priv),
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};
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