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https://github.com/brain-hackers/u-boot-brain
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153 lines
3.8 KiB
C
153 lines
3.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Microchip Technology Inc.
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* Padmarao Begari <padmarao.begari@microchip.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <clk-uclass.h>
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#include <asm/io.h>
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#include <dm/device.h>
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#include <dm/devres.h>
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#include <dm/uclass.h>
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#include <dt-bindings/clock/microchip-mpfs-clock.h>
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#include <linux/err.h>
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#include "mpfs_clk.h"
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#define MPFS_CFG_CLOCK "mpfs_cfg_clock"
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#define REG_CLOCK_CONFIG_CR 0x08
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/* CPU and AXI clock divisors */
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static const struct clk_div_table mpfs_div_cpu_axi_table[] = {
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{ 0, 1 }, { 1, 2 }, { 2, 4 }, { 3, 8 },
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{ 0, 0 }
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};
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/* AHB clock divisors */
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static const struct clk_div_table mpfs_div_ahb_table[] = {
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{ 1, 2 }, { 2, 4}, { 3, 8 },
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{ 0, 0 }
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};
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/**
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* struct mpfs_cfg_clock - per instance of configuration clock
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* @id: index of a configuration clock
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* @name: name of a configuration clock
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* @shift: shift to the divider bit field of a configuration clock
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* @width: width of the divider bit field of a configation clock
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* @table: clock divider table instance
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* @flags: common clock framework flags
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*/
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struct mpfs_cfg_clock {
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unsigned int id;
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const char *name;
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u8 shift;
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u8 width;
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const struct clk_div_table *table;
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unsigned long flags;
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};
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/**
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* struct mpfs_cfg_hw_clock - hardware configuration clock (cpu, axi, ahb)
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* @cfg: configuration clock instance
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* @sys_base: base address of the mpfs system register
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* @prate: the pll clock rate
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* @hw: clock instance
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*/
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struct mpfs_cfg_hw_clock {
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struct mpfs_cfg_clock cfg;
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void __iomem *sys_base;
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u32 prate;
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struct clk hw;
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};
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#define to_mpfs_cfg_clk(_hw) container_of(_hw, struct mpfs_cfg_hw_clock, hw)
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static ulong mpfs_cfg_clk_recalc_rate(struct clk *hw)
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{
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struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
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struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
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void __iomem *base_addr = cfg_hw->sys_base;
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unsigned long rate;
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u32 val;
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val = readl(base_addr + REG_CLOCK_CONFIG_CR) >> cfg->shift;
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val &= clk_div_mask(cfg->width);
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rate = cfg_hw->prate / (1u << val);
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hw->rate = rate;
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return rate;
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}
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static ulong mpfs_cfg_clk_set_rate(struct clk *hw, ulong rate)
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{
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struct mpfs_cfg_hw_clock *cfg_hw = to_mpfs_cfg_clk(hw);
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struct mpfs_cfg_clock *cfg = &cfg_hw->cfg;
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void __iomem *base_addr = cfg_hw->sys_base;
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u32 val;
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int divider_setting;
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divider_setting = divider_get_val(rate, cfg_hw->prate, cfg->table, cfg->width, cfg->flags);
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if (divider_setting < 0)
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return divider_setting;
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val = readl(base_addr + REG_CLOCK_CONFIG_CR);
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val &= ~(clk_div_mask(cfg->width) << cfg_hw->cfg.shift);
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val |= divider_setting << cfg->shift;
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writel(val, base_addr + REG_CLOCK_CONFIG_CR);
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return clk_get_rate(hw);
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}
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#define CLK_CFG(_id, _name, _shift, _width, _table, _flags) { \
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.cfg.id = _id, \
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.cfg.name = _name, \
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.cfg.shift = _shift, \
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.cfg.width = _width, \
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.cfg.table = _table, \
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.cfg.flags = _flags, \
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}
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static struct mpfs_cfg_hw_clock mpfs_cfg_clks[] = {
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CLK_CFG(CLK_CPU, "clk_cpu", 0, 2, mpfs_div_cpu_axi_table, 0),
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CLK_CFG(CLK_AXI, "clk_axi", 2, 2, mpfs_div_cpu_axi_table, 0),
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CLK_CFG(CLK_AHB, "clk_ahb", 4, 2, mpfs_div_ahb_table, 0),
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};
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int mpfs_clk_register_cfgs(void __iomem *base, u32 clk_rate,
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const char *parent_name)
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{
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int ret;
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int i, id, num_clks;
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const char *name;
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struct clk *hw;
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num_clks = ARRAY_SIZE(mpfs_cfg_clks);
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for (i = 0; i < num_clks; i++) {
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hw = &mpfs_cfg_clks[i].hw;
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mpfs_cfg_clks[i].sys_base = base;
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mpfs_cfg_clks[i].prate = clk_rate;
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name = mpfs_cfg_clks[i].cfg.name;
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ret = clk_register(hw, MPFS_CFG_CLOCK, name, parent_name);
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if (ret)
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ERR_PTR(ret);
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id = mpfs_cfg_clks[i].cfg.id;
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clk_dm(id, hw);
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}
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return 0;
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}
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const struct clk_ops mpfs_cfg_clk_ops = {
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.set_rate = mpfs_cfg_clk_set_rate,
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.get_rate = mpfs_cfg_clk_recalc_rate,
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};
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U_BOOT_DRIVER(mpfs_cfg_clock) = {
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.name = MPFS_CFG_CLOCK,
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.id = UCLASS_CLK,
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.ops = &mpfs_cfg_clk_ops,
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};
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