u-boot-brain/arch/arm/include/asm/arch-armada8k/cache_llc.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright (C) 2016 Marvell International Ltd.
 * https://spdx.org/licenses
 */

#ifndef _CACHE_LLC_H_
#define _CACHE_LLC_H_

/* Armada-7K/8K last level cache */

#define MVEBU_A8K_REGS_BASE_MSB		0xf000
#define LLC_BASE_ADDR			0x8000
#define LLC_CACHE_SYNC			0x700
#define LLC_CACHE_SYNC_COMPLETE		0x730
#define LLC_FLUSH_BY_WAY		0x7fc
#define LLC_WAY_MASK			0xffffffff
#define LLC_CACHE_SYNC_MASK		0x1

#endif	/* _CACHE_LLC_H_ */
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> 2018-05-07 06:58:06 +09:00			`/* SPDX-License-Identifier: GPL-2.0 */`
arm64: mvebu: Add L3 cache flush functionality to A8K family Add missing L3 cache flush functionality which absence prevents Linux kernel from normal boot in case the L3 cache is enabled by ATF. The L3 cache is named the "last level" cache in order to keep the terminology similar to the ATF code. This cache should not be disabled by u-boot since the Linux kernel cannot activate it, so it is activates at ATF stage. However the cache flush is required for preventing data corruption after disabling the MMU and the data cache before passing control to the loaded Linux image. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Cc: Stefan Roese <sr@denx.de> Cc: Nadav Haklai <nadavh@marvell.com> Cc: Neta Zur Hershkovits <neta@marvell.com> Cc: Omri Itach <omrii@marvell.com> Cc: Igal Liberman <igall@marvell.com> Cc: Haim Boot <hayim@marvell.com> Cc: Hanna Hawa <hannah@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> 2016-12-05 01:34:13 +09:00			`/*`
			`* Copyright (C) 2016 Marvell International Ltd.`
			`* https://spdx.org/licenses`
			`*/`

			`#ifndef _CACHE_LLC_H_`
			`#define _CACHE_LLC_H_`

			`/* Armada-7K/8K last level cache */`

			`#define MVEBU_A8K_REGS_BASE_MSB 0xf000`
			`#define LLC_BASE_ADDR 0x8000`
			`#define LLC_CACHE_SYNC 0x700`
			`#define LLC_CACHE_SYNC_COMPLETE 0x730`
			`#define LLC_FLUSH_BY_WAY 0x7fc`
			`#define LLC_WAY_MASK 0xffffffff`
			`#define LLC_CACHE_SYNC_MASK 0x1`

			`#endif /* _CACHE_LLC_H_ */`