2008-11-20 17:57:47 +09:00
|
|
|
/*
|
|
|
|
* Copyright (C) 2006 Freescale Semiconductor, Inc.
|
|
|
|
* Dave Liu <daveliu@freescale.com>
|
|
|
|
*
|
|
|
|
* Copyright (C) 2007 Logic Product Development, Inc.
|
|
|
|
* Peter Barada <peterb@logicpd.com>
|
|
|
|
*
|
|
|
|
* Copyright (C) 2007 MontaVista Software, Inc.
|
|
|
|
* Anton Vorontsov <avorontsov@ru.mvista.com>
|
|
|
|
*
|
|
|
|
* (C) Copyright 2008
|
|
|
|
* Heiko Schocher, DENX Software Engineering, hs@denx.de.
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU General Public License as
|
|
|
|
* published by the Free Software Foundation; either version 2 of
|
|
|
|
* the License, or (at your option) any later version.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
|
|
|
#include <ioports.h>
|
|
|
|
#include <mpc83xx.h>
|
|
|
|
#include <i2c.h>
|
|
|
|
#include <miiphy.h>
|
|
|
|
#include <asm/io.h>
|
|
|
|
#include <asm/mmu.h>
|
2009-02-24 19:30:48 +09:00
|
|
|
#include <asm/processor.h>
|
2008-11-20 17:57:47 +09:00
|
|
|
#include <pci.h>
|
|
|
|
#include <libfdt.h>
|
|
|
|
|
2008-11-21 16:29:40 +09:00
|
|
|
#include "../common/common.h"
|
|
|
|
|
2008-11-20 17:57:47 +09:00
|
|
|
const qe_iop_conf_t qe_iop_conf_tab[] = {
|
|
|
|
/* port pin dir open_drain assign */
|
|
|
|
|
|
|
|
/* MDIO */
|
|
|
|
{0, 1, 3, 0, 2}, /* MDIO */
|
|
|
|
{0, 2, 1, 0, 1}, /* MDC */
|
|
|
|
|
|
|
|
/* UCC4 - UEC */
|
|
|
|
{1, 14, 1, 0, 1}, /* TxD0 */
|
|
|
|
{1, 15, 1, 0, 1}, /* TxD1 */
|
|
|
|
{1, 20, 2, 0, 1}, /* RxD0 */
|
|
|
|
{1, 21, 2, 0, 1}, /* RxD1 */
|
|
|
|
{1, 18, 1, 0, 1}, /* TX_EN */
|
|
|
|
{1, 26, 2, 0, 1}, /* RX_DV */
|
|
|
|
{1, 27, 2, 0, 1}, /* RX_ER */
|
|
|
|
{1, 24, 2, 0, 1}, /* COL */
|
|
|
|
{1, 25, 2, 0, 1}, /* CRS */
|
|
|
|
{2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
|
|
|
|
{2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
|
|
|
|
|
|
|
|
/* DUART - UART2 */
|
|
|
|
{5, 0, 1, 0, 2}, /* UART2_SOUT */
|
|
|
|
{5, 2, 1, 0, 1}, /* UART2_RTS */
|
|
|
|
{5, 3, 2, 0, 2}, /* UART2_SIN */
|
|
|
|
{5, 1, 2, 0, 3}, /* UART2_CTS */
|
|
|
|
|
|
|
|
/* END of table */
|
|
|
|
{0, 0, 0, 0, QE_IOP_TAB_END},
|
|
|
|
};
|
|
|
|
|
2011-03-16 00:52:29 +09:00
|
|
|
static int board_init_i2c_busses(void)
|
2009-02-24 19:30:34 +09:00
|
|
|
{
|
|
|
|
I2C_MUX_DEVICE *dev = NULL;
|
|
|
|
uchar *buf;
|
|
|
|
|
|
|
|
/* Set up the Bus for the DTTs */
|
2011-03-16 00:52:29 +09:00
|
|
|
buf = (unsigned char *) getenv("dtt_bus");
|
2009-02-24 19:30:34 +09:00
|
|
|
if (buf != NULL)
|
2011-03-16 00:52:29 +09:00
|
|
|
dev = i2c_mux_ident_muxstring(buf);
|
2009-02-24 19:30:34 +09:00
|
|
|
if (dev == NULL) {
|
2011-03-16 00:52:29 +09:00
|
|
|
printf("Error couldn't add Bus for DTT\n");
|
|
|
|
printf("please setup dtt_bus to where your\n");
|
|
|
|
printf("DTT is found.\n");
|
2009-02-24 19:30:34 +09:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-03-16 00:52:29 +09:00
|
|
|
int board_early_init_r(void)
|
2008-11-20 17:57:47 +09:00
|
|
|
{
|
2011-03-16 00:52:29 +09:00
|
|
|
struct km_bec_fpga *base = (struct km_bec_fpga *)CONFIG_SYS_PIGGY_BASE;
|
2009-02-24 19:30:48 +09:00
|
|
|
unsigned short svid;
|
2008-11-20 17:57:47 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Because of errata in the UCCs, we have to write to the reserved
|
|
|
|
* registers to slow the clocks down.
|
|
|
|
*/
|
2011-03-16 00:52:29 +09:00
|
|
|
svid = SVR_REV(mfspr(SVR));
|
2009-02-24 19:30:48 +09:00
|
|
|
switch (svid) {
|
|
|
|
case 0x0020:
|
2011-03-16 00:52:29 +09:00
|
|
|
/*
|
|
|
|
* MPC8360ECE.pdf QE_ENET10 table 4:
|
|
|
|
* IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
|
|
|
|
* IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
|
|
|
|
*/
|
2009-02-24 19:30:48 +09:00
|
|
|
setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
|
|
|
|
break;
|
|
|
|
case 0x0021:
|
2011-03-16 00:52:29 +09:00
|
|
|
/*
|
|
|
|
* MPC8360ECE.pdf QE_ENET10 table 4:
|
|
|
|
* IMMR + 0x14AC[24:27] = 1010
|
|
|
|
*/
|
2009-02-24 19:30:48 +09:00
|
|
|
clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
|
|
|
|
0x00000050, 0x000000a0);
|
|
|
|
break;
|
|
|
|
}
|
2008-11-20 17:57:47 +09:00
|
|
|
/* enable the PHY on the PIGGY */
|
2011-03-16 00:52:29 +09:00
|
|
|
setbits_8(&base->pgy_eth, 0x01);
|
2010-01-07 16:55:50 +09:00
|
|
|
/* enable the Unit LED (green) */
|
2011-03-16 00:52:29 +09:00
|
|
|
setbits_8(&base->oprth, WRL_BOOT);
|
2010-01-07 16:55:50 +09:00
|
|
|
/* take FE/GbE PHYs out of reset */
|
2011-03-16 00:52:29 +09:00
|
|
|
setbits_8(&base->prst, 0x1c);
|
2008-11-20 17:57:47 +09:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-03-16 00:52:29 +09:00
|
|
|
int misc_init_r(void)
|
2009-02-24 19:30:34 +09:00
|
|
|
{
|
|
|
|
/* add board specific i2c busses */
|
2011-03-16 00:52:29 +09:00
|
|
|
board_init_i2c_busses();
|
2009-02-24 19:30:34 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2008-11-20 17:57:47 +09:00
|
|
|
int fixed_sdram(void)
|
|
|
|
{
|
2011-03-16 00:52:29 +09:00
|
|
|
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
2008-11-20 17:57:47 +09:00
|
|
|
u32 msize = 0;
|
|
|
|
u32 ddr_size;
|
|
|
|
u32 ddr_size_log2;
|
|
|
|
|
2011-03-16 00:52:29 +09:00
|
|
|
out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
|
|
|
|
out_be32(&im->ddr.csbnds[0].csbnds, CONFIG_SYS_DDR_CS0_BNDS);
|
|
|
|
out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
|
|
|
|
out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
|
|
|
|
out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
|
|
|
|
out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
|
|
|
|
out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
|
|
|
|
out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
|
|
|
|
out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
|
|
|
|
out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
|
|
|
|
out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
|
|
|
|
out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
|
|
|
|
out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
|
|
|
|
udelay(200);
|
|
|
|
out_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
|
2008-11-20 17:57:47 +09:00
|
|
|
|
2009-02-24 19:30:40 +09:00
|
|
|
msize = CONFIG_SYS_DDR_SIZE << 20;
|
2011-03-16 00:52:29 +09:00
|
|
|
disable_addr_trans();
|
|
|
|
msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
|
|
|
|
enable_addr_trans();
|
2009-02-24 19:30:40 +09:00
|
|
|
msize /= (1024 * 1024);
|
|
|
|
if (CONFIG_SYS_DDR_SIZE != msize) {
|
|
|
|
for (ddr_size = msize << 20, ddr_size_log2 = 0;
|
2011-03-16 00:52:29 +09:00
|
|
|
(ddr_size > 1);
|
|
|
|
ddr_size = ddr_size >> 1, ddr_size_log2++)
|
2009-02-24 19:30:40 +09:00
|
|
|
if (ddr_size & 1)
|
|
|
|
return -1;
|
2011-03-16 00:52:29 +09:00
|
|
|
out_be32(&im->sysconf.ddrlaw[0].ar,
|
|
|
|
(LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
|
|
|
|
out_be32(&im->ddr.csbnds[0].csbnds,
|
|
|
|
(((msize / 16) - 1) & 0xff));
|
2009-02-24 19:30:40 +09:00
|
|
|
}
|
|
|
|
|
2008-11-20 17:57:47 +09:00
|
|
|
return msize;
|
|
|
|
}
|
|
|
|
|
2011-03-16 00:52:29 +09:00
|
|
|
phys_size_t initdram(int board_type)
|
2008-11-20 17:57:47 +09:00
|
|
|
{
|
2011-03-16 00:52:29 +09:00
|
|
|
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
|
2008-11-20 17:57:47 +09:00
|
|
|
u32 msize = 0;
|
|
|
|
|
2011-03-16 00:52:29 +09:00
|
|
|
if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
|
2008-11-20 17:57:47 +09:00
|
|
|
return -1;
|
|
|
|
|
2011-03-16 00:52:29 +09:00
|
|
|
out_be32(&im->sysconf.ddrlaw[0].bar,
|
|
|
|
CONFIG_SYS_DDR_BASE & LAWBAR_BAR);
|
|
|
|
msize = fixed_sdram();
|
2008-11-20 17:57:47 +09:00
|
|
|
|
2009-07-01 07:15:50 +09:00
|
|
|
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
|
2008-11-20 17:57:47 +09:00
|
|
|
/*
|
|
|
|
* Initialize DDR ECC byte
|
|
|
|
*/
|
2011-03-16 00:52:29 +09:00
|
|
|
ddr_enable_ecc(msize * 1024 * 1024);
|
2008-11-20 17:57:47 +09:00
|
|
|
#endif
|
|
|
|
|
|
|
|
/* return total bus SDRAM size(bytes) -- DDR */
|
|
|
|
return (msize * 1024 * 1024);
|
|
|
|
}
|
|
|
|
|
2011-03-16 00:52:29 +09:00
|
|
|
int checkboard(void)
|
2008-11-20 17:57:47 +09:00
|
|
|
{
|
2011-03-16 00:52:29 +09:00
|
|
|
puts("Board: Keymile kmeter1");
|
|
|
|
if (ethernet_present())
|
|
|
|
puts(" with PIGGY.");
|
|
|
|
puts("\n");
|
2008-11-20 17:57:47 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#if defined(CONFIG_OF_BOARD_SETUP)
|
2009-07-09 19:04:18 +09:00
|
|
|
/*
|
2010-01-07 16:55:50 +09:00
|
|
|
* update property in the blob
|
2009-07-09 19:04:18 +09:00
|
|
|
*/
|
2011-03-16 00:52:29 +09:00
|
|
|
void ft_blob_update(void *blob, bd_t *bd)
|
2009-07-09 19:04:18 +09:00
|
|
|
{
|
2010-01-07 16:55:50 +09:00
|
|
|
/* no board specific update */
|
2009-07-09 19:04:18 +09:00
|
|
|
}
|
|
|
|
|
|
|
|
|
2011-03-16 00:52:29 +09:00
|
|
|
void ft_board_setup(void *blob, bd_t *bd)
|
2008-11-20 17:57:47 +09:00
|
|
|
{
|
|
|
|
ft_cpu_setup (blob, bd);
|
2009-07-09 19:04:18 +09:00
|
|
|
ft_blob_update (blob, bd);
|
2008-11-20 17:57:47 +09:00
|
|
|
}
|
|
|
|
#endif
|
2009-02-24 19:30:34 +09:00
|
|
|
|
|
|
|
#if defined(CONFIG_HUSH_INIT_VAR)
|
2011-03-16 00:52:29 +09:00
|
|
|
int hush_init_var(void)
|
2009-02-24 19:30:34 +09:00
|
|
|
{
|
2011-03-16 00:52:29 +09:00
|
|
|
ivm_read_eeprom();
|
2009-02-24 19:30:34 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
#endif
|