u-boot-brain/arch/arm/cpu/armv7/mx7ulp/Makefile

#
# (C) Copyright 2016 Freescale Semiconductor, Inc.
#
# SPDX-License-Identifier:	GPL-2.0+
#
#

obj-y	:= clock.o iomux.o pcc.o scg.o
imx: mx7ulp: add iomux driver to support IOMUXC0 and IOMUXC1 Add a new driver under ULP directory to support its IOMUXC controllers. The ULP has two IOMUXC, the IOMUXC0 is used for M4 domain, while IOMUXC1 is for A7. We set IOMUXC1 as the default IOMUX in this driver. Any pins in IOMUXC0 needs to configure with IOMUX_CONFIG_MPORTS in its mux_mode field. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by : Stefano Babic <sbabic@denx.de> 2017-02-22 17:21:41 +09:00			`#`
			`# (C) Copyright 2016 Freescale Semiconductor, Inc.`
			`#`
			`# SPDX-License-Identifier: GPL-2.0+`
			`#`
			`#`

imx: mx7ulp: Add clock framework and functions Add a clock framework to support SCG1/PCC2/PCC3 for A7 to support get/set clock source, divider, clock rate and parent source. Users need to include pcc.h to use the APIs to for peripherals clock. Each peripheral clock is defined in enum pcc_clk type. SCG relevants APIs are defined in scg.h which supports clock rate get, PLL/PFD enablement and settings, and all SCG clock initialization. User need use enum scg_clk to access each clock source. In clock.c, we initialize necessary clocks at u-boot s_init and implement the clock functions used by driver modules to operate clocks dynamically. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Cc: Stefano Babic <sbabic@denx.de> 2017-02-22 17:21:42 +09:00			`obj-y := clock.o iomux.o pcc.o scg.o`