2009-02-06 11:40:57 +09:00
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/*
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2011-01-14 01:09:27 +09:00
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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2009-02-06 11:40:57 +09:00
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*
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2013-07-08 16:37:19 +09:00
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* SPDX-License-Identifier: GPL-2.0+
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2009-02-06 11:40:57 +09:00
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*/
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#ifndef _ASM_CONFIG_H_
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#define _ASM_CONFIG_H_
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2011-01-19 18:05:26 +09:00
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#ifdef CONFIG_MPC85xx
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#include <asm/config_mpc85xx.h>
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2013-10-01 01:22:09 +09:00
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#define CONFIG_SYS_FSL_DDR
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2011-01-19 18:05:26 +09:00
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#endif
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#ifdef CONFIG_MPC86xx
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#include <asm/config_mpc86xx.h>
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2013-10-01 01:22:09 +09:00
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#define CONFIG_SYS_FSL_DDR
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#endif
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#ifdef CONFIG_MPC83xx
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#define CONFIG_SYS_FSL_DDR
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2011-01-19 18:05:26 +09:00
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#endif
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2012-08-17 18:00:54 +09:00
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#ifndef HWCONFIG_BUFFER_SIZE
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#define HWCONFIG_BUFFER_SIZE 256
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#endif
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2011-04-26 17:31:16 +09:00
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/* CONFIG_HARD_SPI triggers SPI bus initialization in PowerPC */
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#if defined(CONFIG_MPC8XXX_SPI) || defined(CONFIG_FSL_ESPI)
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# ifndef CONFIG_HARD_SPI
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# define CONFIG_HARD_SPI
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# endif
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#endif
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2009-11-04 01:35:59 +09:00
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#define CONFIG_LMB
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2010-10-14 04:57:35 +09:00
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#define CONFIG_SYS_BOOT_RAMDISK_HIGH
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#define CONFIG_SYS_BOOT_GET_CMDLINE
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#define CONFIG_SYS_BOOT_GET_KBD
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2009-11-04 01:35:59 +09:00
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2009-02-06 11:40:58 +09:00
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#ifndef CONFIG_MAX_MEM_MAPPED
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2011-08-27 03:32:44 +09:00
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#if defined(CONFIG_4xx) || \
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defined(CONFIG_E500) || \
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defined(CONFIG_MPC86xx) || \
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defined(CONFIG_E300)
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2009-02-06 11:40:58 +09:00
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#define CONFIG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
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#else
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2009-02-11 17:37:12 +09:00
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#define CONFIG_MAX_MEM_MAPPED (256 << 20)
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2009-02-06 11:40:58 +09:00
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#endif
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#endif
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2009-07-15 14:01:08 +09:00
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/* Check if boards need to enable FSL DMA engine for SDRAM init */
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#if !defined(CONFIG_FSL_DMA) && defined(CONFIG_DDR_ECC)
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#if (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)) || \
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((defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)) && \
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!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER))
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2009-07-01 07:15:40 +09:00
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#define CONFIG_FSL_DMA
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2009-02-06 11:40:57 +09:00
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#endif
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2009-07-01 07:15:40 +09:00
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#endif
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2011-01-19 18:05:26 +09:00
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#ifndef CONFIG_MAX_CPUS
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2009-03-19 16:39:17 +09:00
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#define CONFIG_MAX_CPUS 1
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2009-07-31 15:38:14 +09:00
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#endif
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2009-10-24 05:55:47 +09:00
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/*
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* Provide a default boot page translation virtual address that lines up with
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* Freescale's default e500 reset page.
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*/
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#if (defined(CONFIG_E500) && defined(CONFIG_MP))
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#ifndef CONFIG_BPTR_VIRT_ADDR
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#define CONFIG_BPTR_VIRT_ADDR 0xfffff000
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#endif
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#endif
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2010-06-02 02:24:27 +09:00
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/*
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* SEC (crypto unit) major compatible version determination
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*/
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2011-01-19 18:05:26 +09:00
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#if defined(CONFIG_MPC83xx)
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2014-12-15 15:00:36 +09:00
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#define CONFIG_SYS_FSL_SEC_BE
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2010-06-02 02:24:27 +09:00
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#endif
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2010-06-18 01:37:20 +09:00
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/* Since so many PPC SOCs have a semi-common LBC, define this here */
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#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
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defined(CONFIG_MPC83xx)
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2011-01-20 19:59:35 +09:00
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#if !defined(CONFIG_FSL_IFC)
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2010-06-18 01:37:20 +09:00
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#define CONFIG_FSL_LBC
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#endif
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2011-01-20 19:59:35 +09:00
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#endif
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2010-06-18 01:37:20 +09:00
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2011-04-08 16:10:54 +09:00
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/* The TSEC driver uses the PHYLIB infrastructure */
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#ifndef CONFIG_PHYLIB
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_PHYLIB
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#include <config_phylib_all_drivers.h>
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#endif /* TSEC_ENET */
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#endif /* !CONFIG_PHYLIB */
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2011-04-13 22:37:44 +09:00
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/* The FMAN driver uses the PHYLIB infrastructure */
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#if defined(CONFIG_FMAN_ENET)
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#define CONFIG_PHYLIB
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#endif
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2010-08-08 08:47:05 +09:00
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/* All PPC boards must swap IDE bytes */
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#define CONFIG_IDE_SWAP_IO
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2009-07-01 07:15:40 +09:00
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#endif /* _ASM_CONFIG_H_ */
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