2015-04-21 20:38:20 +09:00
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if ARCH_SOCFPGA
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2019-04-10 04:02:05 +09:00
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config NR_DRAM_BANKS
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default 1
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config SPL_STACK_R_ADDR
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default 0x00800000 if TARGET_SOCFPGA_GEN5
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2019-04-10 04:02:06 +09:00
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config SPL_SYS_MALLOC_F_LEN
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default 0x800 if TARGET_SOCFPGA_GEN5
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2017-02-11 10:15:34 +09:00
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config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
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default 0xa2
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2019-04-10 04:02:05 +09:00
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config SYS_MALLOC_F_LEN
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default 0x2000 if TARGET_SOCFPGA_ARRIA10
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default 0x2000 if TARGET_SOCFPGA_GEN5
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config SYS_TEXT_BASE
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default 0x01000040 if TARGET_SOCFPGA_ARRIA10
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default 0x01000040 if TARGET_SOCFPGA_GEN5
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2015-08-03 04:57:57 +09:00
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config TARGET_SOCFPGA_ARRIA5
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bool
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2015-12-03 04:31:25 +09:00
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select TARGET_SOCFPGA_GEN5
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2015-08-03 04:57:57 +09:00
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2017-04-26 03:44:48 +09:00
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config TARGET_SOCFPGA_ARRIA10
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bool
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2019-05-06 10:55:59 +09:00
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select SPL_ALTERA_SDRAM
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2018-07-23 22:55:15 +09:00
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select SPL_BOARD_INIT if SPL
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2018-07-30 22:56:19 +09:00
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select CLK
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select SPL_CLK if SPL
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2018-08-14 01:32:38 +09:00
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select DM_I2C
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2018-08-14 01:32:38 +09:00
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select DM_RESET
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select SPL_DM_RESET if SPL
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2018-08-14 03:06:46 +09:00
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select REGMAP
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select SPL_REGMAP if SPL
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select SYSCON
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select SPL_SYSCON if SPL
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select ETH_DESIGNWARE_SOCFPGA
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2019-04-10 04:02:05 +09:00
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imply FPGA_SOCFPGA
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imply USE_TINY_PRINTF
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2017-04-26 03:44:48 +09:00
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2015-08-03 04:57:57 +09:00
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config TARGET_SOCFPGA_CYCLONE5
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bool
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2015-12-03 04:31:25 +09:00
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select TARGET_SOCFPGA_GEN5
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config TARGET_SOCFPGA_GEN5
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bool
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2019-05-06 10:55:59 +09:00
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select SPL_ALTERA_SDRAM
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2019-04-10 04:02:05 +09:00
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imply FPGA_SOCFPGA
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imply SPL_STACK_R
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imply SPL_SYS_MALLOC_SIMPLE
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imply USE_TINY_PRINTF
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2015-08-03 04:57:57 +09:00
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2018-05-24 01:17:32 +09:00
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config TARGET_SOCFPGA_STRATIX10
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bool
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select ARMV8_MULTIENTRY
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select ARMV8_SET_SMPEN
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2018-07-23 22:55:15 +09:00
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select ARMV8_SPIN_TABLE
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2018-12-20 11:35:16 +09:00
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select FPGA_STRATIX10
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2018-05-24 01:17:32 +09:00
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2015-04-21 20:38:20 +09:00
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choice
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prompt "Altera SOCFPGA board select"
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2015-05-13 04:46:23 +09:00
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optional
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2015-04-21 20:38:20 +09:00
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2017-04-26 03:44:48 +09:00
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config TARGET_SOCFPGA_ARRIA10_SOCDK
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bool "Altera SOCFPGA SoCDK (Arria 10)"
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select TARGET_SOCFPGA_ARRIA10
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2015-08-03 04:57:57 +09:00
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config TARGET_SOCFPGA_ARRIA5_SOCDK
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bool "Altera SOCFPGA SoCDK (Arria V)"
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select TARGET_SOCFPGA_ARRIA5
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2015-04-21 20:38:20 +09:00
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2015-08-03 04:57:57 +09:00
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config TARGET_SOCFPGA_CYCLONE5_SOCDK
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bool "Altera SOCFPGA SoCDK (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2015-04-21 20:38:20 +09:00
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2018-02-25 07:34:00 +09:00
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config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
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bool "Devboards DBM-SoC1 (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2015-11-24 01:06:27 +09:00
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config TARGET_SOCFPGA_EBV_SOCRATES
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bool "EBV SoCrates (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2016-06-07 19:37:23 +09:00
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config TARGET_SOCFPGA_IS1
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bool "IS1 (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2015-12-02 02:09:52 +09:00
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config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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bool "samtec VIN|ING FPGA (Cyclone V)"
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2017-01-23 09:43:11 +09:00
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select BOARD_LATE_INIT
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2015-12-02 02:09:52 +09:00
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select TARGET_SOCFPGA_CYCLONE5
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2016-06-08 09:57:05 +09:00
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config TARGET_SOCFPGA_SR1500
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bool "SR1500 (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2018-05-24 01:17:32 +09:00
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config TARGET_SOCFPGA_STRATIX10_SOCDK
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bool "Intel SOCFPGA SoCDK (Stratix 10)"
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select TARGET_SOCFPGA_STRATIX10
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2015-09-02 07:41:52 +09:00
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config TARGET_SOCFPGA_TERASIC_DE0_NANO
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bool "Terasic DE0-Nano-Atlas (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2017-04-19 00:11:16 +09:00
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config TARGET_SOCFPGA_TERASIC_DE10_NANO
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bool "Terasic DE10-Nano (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2016-11-15 00:07:10 +09:00
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config TARGET_SOCFPGA_TERASIC_DE1_SOC
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bool "Terasic DE1-SoC (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2015-06-22 00:28:53 +09:00
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config TARGET_SOCFPGA_TERASIC_SOCKIT
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bool "Terasic SoCkit (Cyclone V)"
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select TARGET_SOCFPGA_CYCLONE5
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2015-04-21 20:38:20 +09:00
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endchoice
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config SYS_BOARD
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2015-08-11 04:24:53 +09:00
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default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
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2017-04-26 03:44:48 +09:00
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default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
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2015-08-11 04:24:53 +09:00
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default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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2018-02-25 07:34:00 +09:00
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default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
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2015-09-02 07:41:52 +09:00
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default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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2016-11-15 00:07:10 +09:00
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default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
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2017-04-19 00:11:16 +09:00
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default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
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2016-06-07 19:37:23 +09:00
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default "is1" if TARGET_SOCFPGA_IS1
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2015-06-22 00:28:53 +09:00
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default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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2015-11-24 01:06:27 +09:00
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default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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2015-11-18 19:06:09 +09:00
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default "sr1500" if TARGET_SOCFPGA_SR1500
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2018-05-24 01:17:32 +09:00
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default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
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2015-12-02 02:09:52 +09:00
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default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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2015-04-21 20:38:20 +09:00
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config SYS_VENDOR
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2015-08-03 04:57:57 +09:00
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default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
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2017-04-26 03:44:48 +09:00
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default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
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2015-08-03 04:57:57 +09:00
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default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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2018-05-24 01:17:32 +09:00
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default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
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2018-02-25 07:34:00 +09:00
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default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
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2015-11-24 01:06:27 +09:00
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default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
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2015-12-02 02:09:52 +09:00
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default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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2015-09-02 07:41:52 +09:00
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default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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2016-11-15 00:07:10 +09:00
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default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
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2017-04-19 00:11:16 +09:00
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default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
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2015-06-22 00:28:53 +09:00
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default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
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2015-04-21 20:38:20 +09:00
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config SYS_SOC
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default "socfpga"
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config SYS_CONFIG_NAME
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2015-09-23 07:01:32 +09:00
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default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
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2017-04-26 03:44:48 +09:00
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default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
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2015-09-23 07:01:32 +09:00
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default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
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2018-02-25 07:34:00 +09:00
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default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
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2015-09-02 07:41:52 +09:00
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default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
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2016-11-15 00:07:10 +09:00
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default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
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2017-04-19 00:11:16 +09:00
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default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
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2016-06-07 19:37:23 +09:00
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default "socfpga_is1" if TARGET_SOCFPGA_IS1
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2015-06-22 00:28:53 +09:00
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default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
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2015-11-24 01:06:27 +09:00
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default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
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2015-11-18 19:06:09 +09:00
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default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
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2018-05-24 01:17:32 +09:00
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default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
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2015-12-02 02:09:52 +09:00
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default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
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2015-04-21 20:38:20 +09:00
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endif
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