u-boot-brain/drivers/clk/sunxi/Kconfig

config CLK_SUNXI
	bool "Clock support for Allwinner SoCs"
	depends on CLK && ARCH_SUNXI
	select DM_RESET
	default y
	help
	  This enables support for common clock driver API on Allwinner
	  SoCs.

if CLK_SUNXI

config CLK_SUN4I_A10
	bool "Clock driver for Allwinner A10/A20"
	default MACH_SUN4I || MACH_SUN7I
	help
	  This enables common clock driver support for platforms based
	  on Allwinner A10/A20 SoC.

config CLK_SUN5I_A10S
	bool "Clock driver for Allwinner A10s/A13"
	default MACH_SUN5I
	help
	  This enables common clock driver support for platforms based
	  on Allwinner A10s/A13 SoC.

config CLK_SUN8I_H3
	bool "Clock driver for Allwinner H3/H5"
	default MACH_SUNXI_H3_H5
	help
	  This enables common clock driver support for platforms based
	  on Allwinner H3/H5 SoC.

config CLK_SUN50I_A64
	bool "Clock driver for Allwinner A64"
	default MACH_SUN50I
	help
	  This enables common clock driver support for platforms based
	  on Allwinner A64 SoC.

endif # CLK_SUNXI
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> 2018-12-23 01:02:49 +09:00			`config CLK_SUNXI`
			`bool "Clock support for Allwinner SoCs"`
			`depends on CLK && ARCH_SUNXI`
reset: Add Allwinner RESET driver Add common reset driver for all Allwinner SoC's. Since CLK and RESET share common DT compatible, it is CLK driver job is to bind the reset driver. So add CLK bind call on respective SoC driver by passing ccu map descriptor so-that reset deassert, deassert operations held based on ccu reset table defined from CLK driver. Select DM_RESET via CLK_SUNXI, this make hidden section of RESET since CLK and RESET share common DT compatible and code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> 2019-01-19 01:48:13 +09:00			`select DM_RESET`
clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> 2018-12-23 01:02:49 +09:00			`default y`
			`help`
			`This enables support for common clock driver API on Allwinner`
			`SoCs.`

			`if CLK_SUNXI`

clk: sunxi: Add Allwinner A10/A20 CLK driver Add initial clock driver for Allwinner A10/A20. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10/A20, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10/A20, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> 2018-08-02 20:22:37 +09:00			`config CLK_SUN4I_A10`
			`bool "Clock driver for Allwinner A10/A20"`
			`default MACH_SUN4I \|\| MACH_SUN7I`
			`help`
			`This enables common clock driver support for platforms based`
			`on Allwinner A10/A20 SoC.`

clk: sunxi: Add Allwinner A10s/A13 CLK driver Add initial clock driver for Allwinner A10s/A13. - Implement USB ahb and USB clocks via ccu_clk_gate table for A10s/A13, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB resets via ccu_reset table for A10s/A13, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> 2018-08-02 23:24:26 +09:00			`config CLK_SUN5I_A10S`
			`bool "Clock driver for Allwinner A10s/A13"`
			`default MACH_SUN5I`
			`help`
			`This enables common clock driver support for platforms based`
			`on Allwinner A10s/A13 SoC.`

clk: sunxi: Add Allwinner H3/H5 CLK driver Add initial clock driver for Allwinner H3/H5. - Implement USB bus and USB clocks via ccu_clk_gate table for H3/H5, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement USB bus and USB resets via ccu_reset table for H3/H5, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> 2018-08-02 19:13:02 +09:00			`config CLK_SUN8I_H3`
			`bool "Clock driver for Allwinner H3/H5"`
			`default MACH_SUNXI_H3_H5`
			`help`
			`This enables common clock driver support for platforms based`
			`on Allwinner H3/H5 SoC.`

clk: Add Allwinner A64 CLK driver Add initial clock driver for Allwinner A64. Implement USB clock enable and disable functions for OHCI, EHCI, OTG and USBPHY gate and clock registers via ccu clk gate table. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> 2018-12-23 01:02:49 +09:00			`config CLK_SUN50I_A64`
			`bool "Clock driver for Allwinner A64"`
			`default MACH_SUN50I`
			`help`
			`This enables common clock driver support for platforms based`
			`on Allwinner A64 SoC.`

			`endif # CLK_SUNXI`