mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 17:08:52 +09:00
203 lines
5.1 KiB
C
203 lines
5.1 KiB
C
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/*
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* Clock setup for SMDK5250 board based on EXYNOS5
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*
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* Copyright (C) 2012 Samsung Electronics
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/gpio.h>
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#include "setup.h"
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void system_clock_init()
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{
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struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
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/*
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* MUX_APLL_SEL[0]: FINPLL = 0
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* MUX_CPU_SEL[6]: MOUTAPLL = 0
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* MUX_HPM_SEL[20]: MOUTAPLL = 0
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*/
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writel(0x0, &clk->src_cpu);
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/* MUX_MPLL_SEL[8]: FINPLL = 0 */
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writel(0x0, &clk->src_core1);
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/*
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* VPLLSRC_SEL[0]: FINPLL = 0
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* MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0
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*/
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writel(0x0, &clk->src_top2);
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/* MUX_BPLL_SEL[0]: FINPLL = 0 */
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writel(0x0, &clk->src_cdrex);
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/* MUX_ACLK_* Clock Selection */
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writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
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/* MUX_ACLK_* Clock Selection */
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writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
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/* MUX_ACLK_* Clock Selection */
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writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
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/* MUX_PWI_SEL[19:16]: SCLKMPLL = 6 */
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writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
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/* MUX_ATCLK_LEX[0]: ACLK_200 = 0 */
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writel(CLK_SRC_LEX_VAL, &clk->src_lex);
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/* UART [0-5]: SCLKMPLL = 6 */
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writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
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/* Set Clock Ratios */
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writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
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/* Set COPY and HPM Ratio */
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writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
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/* CORED_RATIO, COREP_RATIO */
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writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
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/* PWI_RATIO[11:8], DVSEM_RATIO[22:16], DPM_RATIO[24:20] */
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writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
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/* ACLK_*_RATIO */
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writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
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/* ACLK_*_RATIO */
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writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
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/* CDREX Ratio */
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writel(CLK_DIV_CDREX_INIT_VAL, &clk->div_cdrex);
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/* MCLK_EFPHY_RATIO[3:0] */
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writel(CLK_DIV_CDREX2_VAL, &clk->div_cdrex2);
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/* {PCLK[4:6]|ATCLK[10:8]}_RATIO */
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writel(CLK_DIV_LEX_VAL, &clk->div_lex);
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/* PCLK_R0X_RATIO[3:0] */
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writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
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/* PCLK_R1X_RATIO[3:0] */
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writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
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/* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */
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writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
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/* UART[0-4] */
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writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
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/* PWM_RATIO[3:0] */
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writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
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/* SATA_RATIO, USB_DRD_RATIO */
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writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
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/* MMC[0-1] */
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writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
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/* MMC[2-3] */
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writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
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/* MMC[4] */
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writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
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/* ACLK|PLCK_ACP_RATIO */
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writel(CLK_DIV_ACP_VAL, &clk->div_acp);
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/* ISPDIV0_RATIO, ISPDIV1_RATIO */
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writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
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/* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */
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writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
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/* MPWMDIV_RATIO */
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writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
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/* PLL locktime */
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writel(APLL_LOCK_VAL, &clk->apll_lock);
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writel(MPLL_LOCK_VAL, &clk->mpll_lock);
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writel(BPLL_LOCK_VAL, &clk->bpll_lock);
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writel(CPLL_LOCK_VAL, &clk->cpll_lock);
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writel(EPLL_LOCK_VAL, &clk->epll_lock);
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writel(VPLL_LOCK_VAL, &clk->vpll_lock);
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sdelay(0x10000);
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/* Set APLL */
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writel(APLL_CON1_VAL, &clk->apll_con1);
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writel(APLL_CON0_VAL, &clk->apll_con0);
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sdelay(0x30000);
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/* Set MPLL */
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writel(MPLL_CON1_VAL, &clk->mpll_con1);
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writel(MPLL_CON0_VAL, &clk->mpll_con0);
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sdelay(0x30000);
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writel(BPLL_CON1_VAL, &clk->bpll_con1);
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writel(BPLL_CON0_VAL, &clk->bpll_con0);
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sdelay(0x30000);
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/* Set CPLL */
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writel(CPLL_CON1_VAL, &clk->cpll_con1);
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writel(CPLL_CON0_VAL, &clk->cpll_con0);
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sdelay(0x30000);
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/* Set EPLL */
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writel(EPLL_CON2_VAL, &clk->epll_con2);
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writel(EPLL_CON1_VAL, &clk->epll_con1);
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writel(EPLL_CON0_VAL, &clk->epll_con0);
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sdelay(0x30000);
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/* Set VPLL */
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writel(VPLL_CON2_VAL, &clk->vpll_con2);
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writel(VPLL_CON1_VAL, &clk->vpll_con1);
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writel(VPLL_CON0_VAL, &clk->vpll_con0);
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sdelay(0x30000);
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/* Set MPLL */
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/* After Initiallising th PLL select the sources accordingly */
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/* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */
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writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
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/* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */
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writel(CLK_SRC_CORE1_VAL, &clk->src_core1);
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/* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/
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writel(CLK_SRC_CDREX_INIT_VAL, &clk->src_cdrex);
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/*
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* VPLLSRC_SEL[0]: FINPLL = 0
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* MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1
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* MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1
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*/
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writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
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}
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