mirror of
https://github.com/brain-hackers/u-boot-brain
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214 lines
5.3 KiB
C
214 lines
5.3 KiB
C
![]() |
/*
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* Xilinx SPI driver
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*
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* supports 8 bit SPI transfers only, with or w/o FIFO
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*
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* based on bfin_spi.c, by way of altera_spi.c
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* Copyright (c) 2005-2008 Analog Devices Inc.
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* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
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* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
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* Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
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*
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* Licensed under the GPL-2 or later.
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*
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* [0]: http://www.xilinx.com/support/documentation
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*
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* [S]: [0]/ip_documentation/xps_spi.pdf
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* [0]/ip_documentation/axi_spi_ds742.pdf
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*/
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#include <config.h>
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include "xilinx_spi.h"
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#ifndef CONFIG_SYS_XILINX_SPI_LIST
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#define CONFIG_SYS_XILINX_SPI_LIST { CONFIG_SYS_SPI_BASE }
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#endif
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#ifndef CONFIG_XILINX_SPI_IDLE_VAL
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#define CONFIG_XILINX_SPI_IDLE_VAL 0xff
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#endif
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#define XILSPI_SPICR_DFLT_ON (SPICR_MANUAL_SS | \
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SPICR_MASTER_MODE | \
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SPICR_SPE)
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#define XILSPI_SPICR_DFLT_OFF (SPICR_MASTER_INHIBIT | \
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SPICR_MANUAL_SS)
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#define XILSPI_MAX_XFER_BITS 8
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static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
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__attribute__((weak))
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32;
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}
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__attribute__((weak))
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void spi_cs_activate(struct spi_slave *slave)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr);
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}
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__attribute__((weak))
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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writel(SPISSR_OFF, &xilspi->regs->spissr);
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}
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void spi_init(void)
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{
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/* do nothing */
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}
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void spi_set_speed(struct spi_slave *slave, uint hz)
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{
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/* xilinx spi core does not support programmable speed */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct xilinx_spi_slave *xilspi;
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if (!spi_cs_is_valid(bus, cs)) {
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printf("XILSPI error: %s: unsupported bus %d / cs %d\n",
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__func__, bus, cs);
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return NULL;
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}
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xilspi = malloc(sizeof(*xilspi));
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if (!xilspi) {
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printf("XILSPI error: %s: malloc of SPI structure failed\n",
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__func__);
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return NULL;
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}
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xilspi->slave.bus = bus;
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xilspi->slave.cs = cs;
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xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
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xilspi->freq = max_hz;
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xilspi->mode = mode;
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debug("%s: bus:%i cs:%i base:%p mode:%x max_hz:%d\n", __func__,
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bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);
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return &xilspi->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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free(xilspi);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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u32 spicr;
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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writel(SPISSR_OFF, &xilspi->regs->spissr);
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spicr = XILSPI_SPICR_DFLT_ON;
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if (xilspi->mode & SPI_LSB_FIRST)
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spicr |= SPICR_LSB_FIRST;
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if (xilspi->mode & SPI_CPHA)
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spicr |= SPICR_CPHA;
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if (xilspi->mode & SPI_CPOL)
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spicr |= SPICR_CPOL;
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if (xilspi->mode & SPI_LOOP)
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spicr |= SPICR_LOOP;
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writel(spicr, &xilspi->regs->spicr);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs);
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writel(SPISSR_OFF, &xilspi->regs->spissr);
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writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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/* assume spi core configured to do 8 bit transfers */
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unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
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const unsigned char *txp = dout;
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unsigned char *rxp = din;
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unsigned rxecount = 17; /* max. 16 elements in FIFO, leftover 1 */
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debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__,
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slave->bus, slave->cs, bitlen, bytes, flags);
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if (bitlen == 0)
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goto done;
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if (bitlen % XILSPI_MAX_XFER_BITS) {
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printf("XILSPI warning: %s: Not a multiple of %d bits\n",
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__func__, XILSPI_MAX_XFER_BITS);
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flags |= SPI_XFER_END;
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goto done;
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}
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/* empty read buffer */
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while (rxecount && !(readl(&xilspi->regs->spisr) & SPISR_RX_EMPTY)) {
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readl(&xilspi->regs->spidrr);
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rxecount--;
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}
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if (!rxecount) {
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printf("XILSPI error: %s: Rx buffer not empty\n", __func__);
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return -1;
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}
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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while (bytes--) {
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unsigned timeout = /* at least 1usec or greater, leftover 1 */
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xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
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(XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1;
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/* get Tx element from data out buffer and count up */
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unsigned char d = txp ? *txp++ : CONFIG_XILINX_SPI_IDLE_VAL;
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debug("%s: tx:%x ", __func__, d);
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/* write out and wait for processing (receive data) */
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writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr);
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while (timeout && readl(&xilspi->regs->spisr)
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& SPISR_RX_EMPTY) {
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timeout--;
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udelay(1);
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}
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if (!timeout) {
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printf("XILSPI error: %s: Xfer timeout\n", __func__);
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return -1;
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}
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/* read Rx element and push into data in buffer */
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d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK;
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if (rxp)
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*rxp++ = d;
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debug("rx:%x\n", d);
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}
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done:
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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return 0;
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}
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