2012-01-06 21:14:42 +09:00
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/*
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* Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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2016-01-15 12:05:13 +09:00
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* SPDX-License-Identifier: GPL-2.0
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2012-01-06 21:14:42 +09:00
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*/
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#include <common.h>
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#include <asm/io.h>
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2012-09-20 07:50:56 +09:00
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#include <asm/arch/tegra.h>
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2012-01-06 21:14:42 +09:00
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#include <asm/arch/pinmux.h>
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#include <asm/gpio.h>
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2017-01-10 13:32:07 +09:00
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#ifdef CONFIG_MMC_SDHCI_TEGRA
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2012-01-06 21:14:42 +09:00
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/*
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* Routine: pin_mux_mmc
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* Description: setup the pin muxes/tristate values for the SDMMC(s)
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*/
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2013-02-21 21:31:30 +09:00
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void pin_mux_mmc(void)
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2012-01-06 21:14:42 +09:00
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{
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/* SDMMC4: config 3, x8 on 2nd set of pins */
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2014-03-22 03:28:58 +09:00
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pinmux_set_func(PMUX_PINGRP_ATB, PMUX_FUNC_SDIO4);
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pinmux_set_func(PMUX_PINGRP_GMA, PMUX_FUNC_SDIO4);
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pinmux_set_func(PMUX_PINGRP_GME, PMUX_FUNC_SDIO4);
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2012-01-06 21:14:42 +09:00
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2014-03-22 03:28:58 +09:00
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pinmux_tristate_disable(PMUX_PINGRP_ATB);
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pinmux_tristate_disable(PMUX_PINGRP_GMA);
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pinmux_tristate_disable(PMUX_PINGRP_GME);
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2012-01-06 21:14:42 +09:00
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2012-05-16 17:21:01 +09:00
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/* SDIO1: SDIO1_CLK, SDIO1_CMD, SDIO1_DAT[3:0] */
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2014-03-22 03:28:58 +09:00
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pinmux_set_func(PMUX_PINGRP_SDIO1, PMUX_FUNC_SDIO1);
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2012-01-06 21:14:42 +09:00
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2014-03-22 03:28:58 +09:00
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pinmux_tristate_disable(PMUX_PINGRP_SDIO1);
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2012-01-06 21:14:42 +09:00
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/* For power GPIO PV1 */
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2014-03-22 03:28:58 +09:00
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pinmux_tristate_disable(PMUX_PINGRP_UAC);
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2012-05-15 20:58:11 +09:00
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/* For CD GPIO PV5 */
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2014-03-22 03:28:58 +09:00
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pinmux_tristate_disable(PMUX_PINGRP_GPV);
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2012-01-06 21:14:42 +09:00
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}
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#endif
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2012-11-25 20:26:12 +09:00
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2016-01-31 08:37:56 +09:00
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#ifdef CONFIG_DM_VIDEO
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2012-11-25 20:26:12 +09:00
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/* this is a weak define that we are overriding */
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void pin_mux_display(void)
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{
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debug("init display pinmux\n");
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/* EN_VDD_PANEL GPIO A4 */
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2014-03-22 03:28:58 +09:00
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pinmux_tristate_disable(PMUX_PINGRP_DAP2);
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2012-11-25 20:26:12 +09:00
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}
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#endif
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