u-boot-brain/arch/arm/include/asm/gic.h

#ifndef __GIC_V2_H__
#define __GIC_V2_H__

/* register offsets for the ARM generic interrupt controller (GIC) */

#define GIC_DIST_OFFSET		0x1000
#define GICD_CTLR		0x0000
#define GICD_TYPER		0x0004
#define GICD_IGROUPRn		0x0080
#define GICD_SGIR		0x0F00

#define GIC_CPU_OFFSET_A9	0x0100
#define GIC_CPU_OFFSET_A15	0x2000
#define GICC_CTLR		0x0000
#define GICC_PMR		0x0004

#endif
ARM: add assembly routine to switch to non-secure state While actually switching to non-secure state is one thing, another part of this process is to make sure that we still have full access to the interrupt controller (GIC). The GIC is fully aware of secure vs. non-secure state, some registers are banked, others may be configured to be accessible from secure state only. To be as generic as possible, we get the GIC memory mapped address based on the PERIPHBASE value in the CBAR register. Since this register is not architecturally defined, we check the MIDR before to be from an A15 or A7. For CPUs not having the CBAR or boards with wrong information herein we allow providing the base address as a configuration variable. Now that we know the GIC address, we: a) allow private interrupts to be delivered to the core (GICD_IGROUPR0 = 0xFFFFFFFF) b) enable the CPU interface (GICC_CTLR[0] = 1) c) set the priority filter to allow non-secure interrupts (GICC_PMR = 0xFF) Also we allow access to all coprocessor interfaces from non-secure state by writing the appropriate bits in the NSACR register. The generic timer base frequency register is only accessible from secure state, so we have to program it now. Actually this should be done from primary firmware before, but some boards seems to omit this, so if needed we do this here with a board specific value. The Versatile Express board does not need this, so we remove the frequency from the configuration file here. After having switched to non-secure state, we also enable the non-secure GIC CPU interface, since this register is banked. Since we need to call this routine also directly from the smp_pen later (where we don't have any stack), we can only use caller saved registers r0-r3 and r12 to not mess with the compiler. Signed-off-by: Andre Przywara <andre.przywara@linaro.org> 2013-09-20 01:06:41 +09:00			`#ifndef __GIC_V2_H__`
			`#define __GIC_V2_H__`

			`/* register offsets for the ARM generic interrupt controller (GIC) */`

			`#define GIC_DIST_OFFSET 0x1000`
			`#define GICD_CTLR 0x0000`
			`#define GICD_TYPER 0x0004`
			`#define GICD_IGROUPRn 0x0080`
			`#define GICD_SGIR 0x0F00`

			`#define GIC_CPU_OFFSET_A9 0x0100`
			`#define GIC_CPU_OFFSET_A15 0x2000`
			`#define GICC_CTLR 0x0000`
			`#define GICC_PMR 0x0004`

			`#endif`