2012-10-04 15:46:02 +09:00
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/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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2013-07-08 16:37:19 +09:00
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* SPDX-License-Identifier: GPL-2.0+
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2012-10-04 15:46:02 +09:00
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*/
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#include <common.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/io.h>
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2014-11-04 12:25:09 +09:00
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#include <usb.h>
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#include <usb/s3c_udc.h>
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#include <usb_mass_storage.h>
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2014-11-14 02:23:41 +09:00
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#include <micrel.h>
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2012-10-04 15:46:02 +09:00
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#include <netdev.h>
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2014-11-14 02:23:41 +09:00
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#include <phy.h>
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2012-10-04 15:46:02 +09:00
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Print Board information
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*/
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int checkboard(void)
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{
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2014-09-08 21:08:45 +09:00
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puts("BOARD: Altera SoCFPGA Cyclone5 Board\n");
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2012-10-04 15:46:02 +09:00
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return 0;
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}
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/*
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* Initialization function which happen at early stage of c code
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*/
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int board_early_init_f(void)
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{
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return 0;
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}
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/*
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* Miscellaneous platform dependent initialisations
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*/
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int board_init(void)
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{
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2014-09-08 21:08:45 +09:00
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/* Address of boot parameters for ATAG (if ATAG is used) */
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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2012-10-04 15:46:02 +09:00
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return 0;
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}
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2014-11-04 12:25:09 +09:00
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2014-11-14 02:23:41 +09:00
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int board_phy_config(struct phy_device *phydev)
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{
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/*
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* These skew settings for the KSZ9021 ethernet phy is required for ethernet
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* to work reliably on most flavors of cyclone5 boards.
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*/
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ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
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0x0);
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ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW,
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0x0);
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ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
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0xf0f0);
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}
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2014-11-04 12:25:09 +09:00
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#ifdef CONFIG_USB_GADGET
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struct s3c_plat_otg_data socfpga_otg_data = {
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.regs_otg = CONFIG_USB_DWC2_REG_ADDR,
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.usb_gusbcfg = 0x1417,
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};
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int board_usb_init(int index, enum usb_init_type init)
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{
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return s3c_udc_probe(&socfpga_otg_data);
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}
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int g_dnl_board_usb_cable_connected(void)
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{
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return 1;
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}
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#endif
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