2014-10-03 19:21:06 +09:00
|
|
|
/*
|
2015-05-29 17:30:00 +09:00
|
|
|
* Copyright (C) 2011-2015 Masahiro Yamada <yamada.masahiro@socionext.com>
|
2014-10-03 19:21:06 +09:00
|
|
|
*
|
|
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
2015-09-22 00:27:39 +09:00
|
|
|
#include <linux/err.h>
|
2015-05-29 17:30:00 +09:00
|
|
|
#include <linux/io.h>
|
2015-09-22 00:27:39 +09:00
|
|
|
#include <linux/sizes.h>
|
2016-01-09 01:51:13 +09:00
|
|
|
|
|
|
|
#include "../init.h"
|
|
|
|
#include "ddrphy-regs.h"
|
|
|
|
#include "umc-regs.h"
|
2014-10-03 19:21:06 +09:00
|
|
|
|
2016-02-26 14:21:48 +09:00
|
|
|
#define DRAM_CH_NR 2
|
|
|
|
|
2016-02-26 14:21:46 +09:00
|
|
|
enum dram_freq {
|
|
|
|
DRAM_FREQ_1333M,
|
|
|
|
DRAM_FREQ_1600M,
|
|
|
|
DRAM_FREQ_NR,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum dram_size {
|
|
|
|
DRAM_SZ_128M,
|
|
|
|
DRAM_SZ_256M,
|
|
|
|
DRAM_SZ_NR,
|
|
|
|
};
|
|
|
|
|
|
|
|
static u32 umc_cmdctla_plus[DRAM_FREQ_NR] = {0x45990b11, 0x36bb0f17};
|
|
|
|
static u32 umc_cmdctlb_plus[DRAM_FREQ_NR] = {0x16958924, 0x18c6aa24};
|
|
|
|
static u32 umc_spcctla[DRAM_FREQ_NR][DRAM_SZ_NR] = {
|
|
|
|
{0x00240512, 0x00350512},
|
|
|
|
{0x002b0617, 0x003f0617},
|
|
|
|
};
|
|
|
|
static u32 umc_spcctlb[DRAM_FREQ_NR] = {0x00ff0006, 0x00ff0008};
|
|
|
|
static u32 umc_rdatactl[DRAM_FREQ_NR] = {0x000a00ac, 0x000c00ae};
|
|
|
|
|
2016-02-26 14:21:48 +09:00
|
|
|
static int umc_get_rank(int ch)
|
|
|
|
{
|
|
|
|
return ch; /* ch0: rank0, ch1: rank1 for this SoC */
|
|
|
|
}
|
|
|
|
|
2015-01-21 15:06:46 +09:00
|
|
|
static void umc_start_ssif(void __iomem *ssif_base)
|
2014-10-03 19:21:06 +09:00
|
|
|
{
|
|
|
|
writel(0x00000000, ssif_base + 0x0000b004);
|
|
|
|
writel(0xffffffff, ssif_base + 0x0000c004);
|
|
|
|
writel(0x000fffcf, ssif_base + 0x0000c008);
|
|
|
|
writel(0x00000001, ssif_base + 0x0000b000);
|
|
|
|
writel(0x00000001, ssif_base + 0x0000c000);
|
|
|
|
writel(0x03010101, ssif_base + UMC_MDMCHSEL);
|
|
|
|
writel(0x03010100, ssif_base + UMC_DMDCHSEL);
|
|
|
|
|
|
|
|
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_FETCH);
|
|
|
|
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE0);
|
|
|
|
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC0);
|
|
|
|
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC0);
|
|
|
|
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMQUE1);
|
|
|
|
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMWC1);
|
|
|
|
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_COMRC1);
|
|
|
|
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_WC);
|
|
|
|
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_RC);
|
|
|
|
writel(0x00000000, ssif_base + UMC_CLKEN_SSIF_DST);
|
|
|
|
|
|
|
|
writel(0x00000001, ssif_base + UMC_CPURST);
|
|
|
|
writel(0x00000001, ssif_base + UMC_IDSRST);
|
|
|
|
writel(0x00000001, ssif_base + UMC_IXMRST);
|
|
|
|
writel(0x00000001, ssif_base + UMC_MDMRST);
|
|
|
|
writel(0x00000001, ssif_base + UMC_MDDRST);
|
|
|
|
writel(0x00000001, ssif_base + UMC_SIORST);
|
|
|
|
writel(0x00000001, ssif_base + UMC_VIORST);
|
|
|
|
writel(0x00000001, ssif_base + UMC_FRCRST);
|
|
|
|
writel(0x00000001, ssif_base + UMC_RGLRST);
|
|
|
|
writel(0x00000001, ssif_base + UMC_AIORST);
|
|
|
|
writel(0x00000001, ssif_base + UMC_DMDRST);
|
|
|
|
}
|
|
|
|
|
2016-02-26 14:21:46 +09:00
|
|
|
static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
|
2016-02-26 14:21:48 +09:00
|
|
|
int size, int freq, bool ddr3plus)
|
2014-10-03 19:21:06 +09:00
|
|
|
{
|
2016-02-26 14:21:46 +09:00
|
|
|
enum dram_freq freq_e;
|
|
|
|
enum dram_size size_e;
|
|
|
|
|
2016-02-26 14:21:48 +09:00
|
|
|
if (!ddr3plus) {
|
|
|
|
pr_err("DDR3 standard is not supported\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
2016-02-26 14:21:46 +09:00
|
|
|
switch (freq) {
|
|
|
|
case 1333:
|
|
|
|
freq_e = DRAM_FREQ_1333M;
|
|
|
|
break;
|
|
|
|
case 1600:
|
|
|
|
freq_e = DRAM_FREQ_1600M;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
pr_err("unsupported DRAM frequency %d MHz\n", freq);
|
|
|
|
return -EINVAL;
|
2014-10-03 19:21:06 +09:00
|
|
|
}
|
|
|
|
|
2016-02-26 14:21:46 +09:00
|
|
|
switch (size) {
|
|
|
|
case 0:
|
|
|
|
return 0;
|
|
|
|
case 1:
|
|
|
|
size_e = DRAM_SZ_128M;
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
size_e = DRAM_SZ_256M;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
pr_err("unsupported DRAM size\n");
|
|
|
|
return -EINVAL;
|
2014-10-03 19:21:06 +09:00
|
|
|
}
|
|
|
|
|
2016-02-26 14:21:46 +09:00
|
|
|
writel(umc_cmdctla_plus[freq_e], dramcont + UMC_CMDCTLA);
|
|
|
|
writel(umc_cmdctlb_plus[freq_e], dramcont + UMC_CMDCTLB);
|
|
|
|
writel(umc_spcctla[freq_e][size_e], dramcont + UMC_SPCCTLA);
|
|
|
|
writel(umc_spcctlb[freq_e], dramcont + UMC_SPCCTLB);
|
|
|
|
writel(umc_rdatactl[freq_e], dramcont + UMC_RDATACTL_D0);
|
2014-10-03 19:21:06 +09:00
|
|
|
writel(0x04060806, dramcont + UMC_WDATACTL_D0);
|
|
|
|
writel(0x04a02000, dramcont + UMC_DATASET);
|
|
|
|
writel(0x00000000, ca_base + 0x2300);
|
|
|
|
writel(0x00400020, dramcont + UMC_DCCGCTL);
|
|
|
|
writel(0x00000003, dramcont + 0x7000);
|
|
|
|
writel(0x0000000f, dramcont + 0x8000);
|
|
|
|
writel(0x000000c3, dramcont + 0x8004);
|
|
|
|
writel(0x00000071, dramcont + 0x8008);
|
|
|
|
writel(0x0000003b, dramcont + UMC_DICGCTLA);
|
|
|
|
writel(0x020a0808, dramcont + UMC_DICGCTLB);
|
|
|
|
writel(0x00000004, dramcont + UMC_FLOWCTLG);
|
|
|
|
writel(0x80000201, ca_base + 0xc20);
|
|
|
|
writel(0x0801e01e, dramcont + UMC_FLOWCTLA);
|
|
|
|
writel(0x00200000, dramcont + UMC_FLOWCTLB);
|
|
|
|
writel(0x00004444, dramcont + UMC_FLOWCTLC);
|
|
|
|
writel(0x200a0a00, dramcont + UMC_SPCSETB);
|
|
|
|
writel(0x00000000, dramcont + UMC_SPCSETD);
|
|
|
|
writel(0x00000520, dramcont + UMC_DFICUPDCTLA);
|
2016-02-26 14:21:46 +09:00
|
|
|
|
|
|
|
return 0;
|
2014-10-03 19:21:06 +09:00
|
|
|
}
|
|
|
|
|
2016-02-26 14:21:48 +09:00
|
|
|
static int umc_ch_init(void __iomem *dc_base, void __iomem *ca_base,
|
|
|
|
int freq, int size, bool ddr3plus, int ch)
|
2014-10-03 19:21:06 +09:00
|
|
|
{
|
2016-02-26 14:21:48 +09:00
|
|
|
void __iomem *phy_base = dc_base + 0x00001000;
|
|
|
|
int ret;
|
2014-12-19 20:20:52 +09:00
|
|
|
|
2016-02-26 14:21:48 +09:00
|
|
|
umc_dram_init_start(dc_base);
|
|
|
|
umc_dram_init_poll(dc_base);
|
2014-12-19 20:20:52 +09:00
|
|
|
|
2016-02-26 14:21:48 +09:00
|
|
|
writel(0x00000101, dc_base + UMC_DIOCTLA);
|
2014-10-03 19:21:06 +09:00
|
|
|
|
2016-02-26 14:21:48 +09:00
|
|
|
ret = ph1_ld4_ddrphy_init(phy_base, freq, ddr3plus);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-12-19 20:20:52 +09:00
|
|
|
|
2016-02-26 14:21:48 +09:00
|
|
|
ddrphy_prepare_training(phy_base, umc_get_rank(ch));
|
|
|
|
ret = ddrphy_training(phy_base);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2014-12-19 20:20:52 +09:00
|
|
|
|
2016-02-26 14:21:48 +09:00
|
|
|
return umc_dramcont_init(dc_base, ca_base, size, freq, ddr3plus);
|
2014-10-03 19:21:06 +09:00
|
|
|
}
|
|
|
|
|
2015-09-22 00:27:39 +09:00
|
|
|
int ph1_ld4_umc_init(const struct uniphier_board_data *bd)
|
2014-10-03 19:21:06 +09:00
|
|
|
{
|
2016-02-26 14:21:48 +09:00
|
|
|
void __iomem *umc_base = (void __iomem *)0x5b800000;
|
|
|
|
void __iomem *ca_base = umc_base + 0x00001000;
|
|
|
|
void __iomem *dc_base = umc_base + 0x00400000;
|
|
|
|
void __iomem *ssif_base = umc_base;
|
|
|
|
int ch, ret;
|
|
|
|
|
|
|
|
for (ch = 0; ch < DRAM_CH_NR; ch++) {
|
|
|
|
ret = umc_ch_init(dc_base, ca_base, bd->dram_freq,
|
|
|
|
bd->dram_ch[ch].size / SZ_128M,
|
|
|
|
bd->dram_ddr3plus, ch);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("failed to initialize UMC ch%d\n", ch);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
ca_base += 0x00001000;
|
|
|
|
dc_base += 0x00200000;
|
2015-09-22 00:27:39 +09:00
|
|
|
}
|
2016-02-26 14:21:48 +09:00
|
|
|
|
|
|
|
umc_start_ssif(ssif_base);
|
|
|
|
|
|
|
|
return 0;
|
2014-10-03 19:21:06 +09:00
|
|
|
}
|