2018-05-07 06:58:06 +09:00
|
|
|
// SPDX-License-Identifier: GPL-2.0+
|
2008-11-28 21:22:09 +09:00
|
|
|
/*
|
2016-07-01 22:21:46 +09:00
|
|
|
* (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
|
2009-05-25 20:53:16 +09:00
|
|
|
*
|
2008-11-28 21:22:09 +09:00
|
|
|
* (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
|
|
|
|
*
|
|
|
|
* Author: Tor Krill tor@excito.com
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <common.h>
|
2019-08-02 00:46:52 +09:00
|
|
|
#include <env.h>
|
2020-05-11 02:40:05 +09:00
|
|
|
#include <log.h>
|
2008-11-28 21:22:09 +09:00
|
|
|
#include <pci.h>
|
|
|
|
#include <usb.h>
|
|
|
|
#include <asm/io.h>
|
2020-05-11 02:40:11 +09:00
|
|
|
#include <linux/delay.h>
|
2016-04-01 06:12:23 +09:00
|
|
|
#include <usb/ehci-ci.h>
|
2011-03-23 18:50:43 +09:00
|
|
|
#include <hwconfig.h>
|
2014-09-30 14:52:43 +09:00
|
|
|
#include <fsl_usb.h>
|
2014-10-20 20:20:49 +09:00
|
|
|
#include <fdt_support.h>
|
2016-07-01 22:21:46 +09:00
|
|
|
#include <dm.h>
|
2008-11-28 21:22:09 +09:00
|
|
|
|
2009-04-03 19:46:58 +09:00
|
|
|
#include "ehci.h"
|
2008-11-28 21:22:09 +09:00
|
|
|
|
2016-07-01 22:21:46 +09:00
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
|
2014-10-20 20:20:49 +09:00
|
|
|
#ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
|
|
|
|
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
|
|
|
|
#endif
|
|
|
|
|
2018-11-21 16:43:56 +09:00
|
|
|
#if CONFIG_IS_ENABLED(DM_USB)
|
2016-07-01 22:21:46 +09:00
|
|
|
struct ehci_fsl_priv {
|
|
|
|
struct ehci_ctrl ehci;
|
|
|
|
fdt_addr_t hcd_base;
|
|
|
|
char *phy_type;
|
|
|
|
};
|
|
|
|
#endif
|
|
|
|
|
2014-04-07 12:16:14 +09:00
|
|
|
static void set_txfifothresh(struct usb_ehci *, u32);
|
2018-11-21 16:43:56 +09:00
|
|
|
#if CONFIG_IS_ENABLED(DM_USB)
|
2016-07-01 22:21:46 +09:00
|
|
|
static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
|
|
|
|
struct ehci_hccr *hccr, struct ehci_hcor *hcor);
|
|
|
|
#else
|
2016-07-01 22:21:45 +09:00
|
|
|
static int ehci_fsl_init(int index, struct usb_ehci *ehci,
|
|
|
|
struct ehci_hccr *hccr, struct ehci_hcor *hcor);
|
2016-07-01 22:21:46 +09:00
|
|
|
#endif
|
2014-04-07 12:16:14 +09:00
|
|
|
|
2012-10-22 14:18:24 +09:00
|
|
|
/* Check USB PHY clock valid */
|
|
|
|
static int usb_phy_clk_valid(struct usb_ehci *ehci)
|
|
|
|
{
|
|
|
|
if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
|
|
|
|
in_be32(&ehci->prictrl))) {
|
|
|
|
printf("USB PHY clock invalid!\n");
|
|
|
|
return 0;
|
|
|
|
} else {
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-11-21 16:43:56 +09:00
|
|
|
#if CONFIG_IS_ENABLED(DM_USB)
|
2020-12-04 08:55:21 +09:00
|
|
|
static int ehci_fsl_of_to_plat(struct udevice *dev)
|
2016-07-01 22:21:46 +09:00
|
|
|
{
|
|
|
|
struct ehci_fsl_priv *priv = dev_get_priv(dev);
|
|
|
|
const void *prop;
|
|
|
|
|
2017-01-18 08:52:55 +09:00
|
|
|
prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
|
2016-07-01 22:21:46 +09:00
|
|
|
NULL);
|
|
|
|
if (prop) {
|
|
|
|
priv->phy_type = (char *)prop;
|
|
|
|
debug("phy_type %s\n", priv->phy_type);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
|
|
|
|
{
|
|
|
|
struct usb_ehci *ehci = NULL;
|
|
|
|
struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
|
|
|
|
ehci);
|
2019-04-11 20:02:05 +09:00
|
|
|
#ifdef CONFIG_PPC
|
|
|
|
ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
|
|
|
|
#else
|
2016-07-01 22:21:46 +09:00
|
|
|
ehci = (struct usb_ehci *)priv->hcd_base;
|
2019-04-11 20:02:05 +09:00
|
|
|
#endif
|
|
|
|
|
2016-07-01 22:21:46 +09:00
|
|
|
if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
|
|
|
|
return -ENXIO;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct ehci_ops fsl_ehci_ops = {
|
|
|
|
.init_after_reset = ehci_fsl_init_after_reset,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int ehci_fsl_probe(struct udevice *dev)
|
|
|
|
{
|
|
|
|
struct ehci_fsl_priv *priv = dev_get_priv(dev);
|
|
|
|
struct usb_ehci *ehci = NULL;
|
|
|
|
struct ehci_hccr *hccr;
|
|
|
|
struct ehci_hcor *hcor;
|
2018-10-04 16:03:53 +09:00
|
|
|
struct ehci_ctrl *ehci_ctrl = &priv->ehci;
|
2016-07-01 22:21:46 +09:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Get the base address for EHCI controller from the device node
|
|
|
|
*/
|
2020-07-17 14:36:48 +09:00
|
|
|
priv->hcd_base = dev_read_addr(dev);
|
2016-07-01 22:21:46 +09:00
|
|
|
if (priv->hcd_base == FDT_ADDR_T_NONE) {
|
|
|
|
debug("Can't get the EHCI register base address\n");
|
|
|
|
return -ENXIO;
|
|
|
|
}
|
2019-04-11 20:02:05 +09:00
|
|
|
#ifdef CONFIG_PPC
|
|
|
|
ehci = (struct usb_ehci *)lower_32_bits(priv->hcd_base);
|
|
|
|
#else
|
2016-07-01 22:21:46 +09:00
|
|
|
ehci = (struct usb_ehci *)priv->hcd_base;
|
2019-04-11 20:02:05 +09:00
|
|
|
#endif
|
2016-07-01 22:21:46 +09:00
|
|
|
hccr = (struct ehci_hccr *)(&ehci->caplength);
|
|
|
|
hcor = (struct ehci_hcor *)
|
usb: ehci: fsl: Fix some compile warnings.
When enable CONFIG_HAS_FSL_DR_USB, we might encounter below compile
warning, apply this patch can fix it:
drivers/usb/host/ehci-fsl.c:109:4: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
^
drivers/usb/host/ehci-fsl.c:108:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
hcor = (struct ehci_hcor *)
^
drivers/usb/host/ehci-fsl.c:115:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
(u32)hccr, (u32)hcor,
^
include/log.h:131:26: note: in definition of macro 'debug_cond'
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
^~~~~
drivers/usb/host/ehci-fsl.c:115:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
(u32)hccr, (u32)hcor,
^
include/log.h:131:26: note: in definition of macro 'debug_cond'
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
^~~~~
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2017-12-20 11:34:19 +09:00
|
|
|
((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
|
2016-07-01 22:21:46 +09:00
|
|
|
|
2018-10-04 16:03:53 +09:00
|
|
|
ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
|
|
|
|
|
2016-07-01 22:21:46 +09:00
|
|
|
if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
|
|
|
|
return -ENXIO;
|
|
|
|
|
usb: ehci: fsl: Fix some compile warnings.
When enable CONFIG_HAS_FSL_DR_USB, we might encounter below compile
warning, apply this patch can fix it:
drivers/usb/host/ehci-fsl.c:109:4: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
((u32)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
^
drivers/usb/host/ehci-fsl.c:108:9: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
hcor = (struct ehci_hcor *)
^
drivers/usb/host/ehci-fsl.c:115:8: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
(u32)hccr, (u32)hcor,
^
include/log.h:131:26: note: in definition of macro 'debug_cond'
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
^~~~~
drivers/usb/host/ehci-fsl.c:115:19: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
(u32)hccr, (u32)hcor,
^
include/log.h:131:26: note: in definition of macro 'debug_cond'
printf(pr_fmt(fmt), ##args); \
^~~~
drivers/usb/host/ehci-fsl.c:114:2: note: in expansion of macro 'debug'
debug("ehci-fsl: init hccr %x and hcor %x hc_length %d\n",
^~~~~
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
2017-12-20 11:34:19 +09:00
|
|
|
debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
|
|
|
|
(void *)hccr, (void *)hcor,
|
|
|
|
HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
|
2016-07-01 22:21:46 +09:00
|
|
|
|
|
|
|
return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct udevice_id ehci_usb_ids[] = {
|
|
|
|
{ .compatible = "fsl-usb2-mph", },
|
|
|
|
{ .compatible = "fsl-usb2-dr", },
|
|
|
|
{ }
|
|
|
|
};
|
|
|
|
|
|
|
|
U_BOOT_DRIVER(ehci_fsl) = {
|
|
|
|
.name = "ehci_fsl",
|
|
|
|
.id = UCLASS_USB,
|
|
|
|
.of_match = ehci_usb_ids,
|
2020-12-04 08:55:21 +09:00
|
|
|
.of_to_plat = ehci_fsl_of_to_plat,
|
2016-07-01 22:21:46 +09:00
|
|
|
.probe = ehci_fsl_probe,
|
2016-09-06 22:17:34 +09:00
|
|
|
.remove = ehci_deregister,
|
2016-07-01 22:21:46 +09:00
|
|
|
.ops = &ehci_usb_ops,
|
2020-12-04 08:55:18 +09:00
|
|
|
.plat_auto = sizeof(struct usb_platdata),
|
2020-12-04 08:55:17 +09:00
|
|
|
.priv_auto = sizeof(struct ehci_fsl_priv),
|
2016-07-01 22:21:46 +09:00
|
|
|
.flags = DM_FLAG_ALLOC_PRIV_DMA,
|
|
|
|
};
|
|
|
|
#else
|
2008-11-28 21:22:09 +09:00
|
|
|
/*
|
|
|
|
* Create the appropriate control structures to manage
|
|
|
|
* a new EHCI host controller.
|
|
|
|
*
|
|
|
|
* Excerpts from linux ehci fsl driver.
|
|
|
|
*/
|
2013-10-11 07:27:57 +09:00
|
|
|
int ehci_hcd_init(int index, enum usb_init_type init,
|
|
|
|
struct ehci_hccr **hccr, struct ehci_hcor **hcor)
|
2008-11-28 21:22:09 +09:00
|
|
|
{
|
2018-10-04 16:03:53 +09:00
|
|
|
struct ehci_ctrl *ehci_ctrl = container_of(hccr,
|
|
|
|
struct ehci_ctrl, hccr);
|
2013-09-12 20:05:49 +09:00
|
|
|
struct usb_ehci *ehci = NULL;
|
2016-07-01 22:21:45 +09:00
|
|
|
|
|
|
|
switch (index) {
|
|
|
|
case 0:
|
|
|
|
ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
|
|
|
|
break;
|
|
|
|
case 1:
|
|
|
|
ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
printf("ERROR: wrong controller index!!\n");
|
|
|
|
return -EINVAL;
|
|
|
|
};
|
|
|
|
|
|
|
|
*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
|
|
|
|
*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
|
|
|
|
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
|
|
|
|
|
2018-10-04 16:03:53 +09:00
|
|
|
ehci_ctrl->has_fsl_erratum_a005275 = has_erratum_a005275();
|
|
|
|
|
2016-07-01 22:21:45 +09:00
|
|
|
return ehci_fsl_init(index, ehci, *hccr, *hcor);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Destroy the appropriate control structures corresponding
|
|
|
|
* the the EHCI host controller.
|
|
|
|
*/
|
|
|
|
int ehci_hcd_stop(int index)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
2016-07-01 22:21:46 +09:00
|
|
|
#endif
|
2016-07-01 22:21:45 +09:00
|
|
|
|
2018-11-21 16:43:56 +09:00
|
|
|
#if CONFIG_IS_ENABLED(DM_USB)
|
2016-07-01 22:21:46 +09:00
|
|
|
static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
|
|
|
|
struct ehci_hccr *hccr, struct ehci_hcor *hcor)
|
|
|
|
#else
|
2016-07-01 22:21:45 +09:00
|
|
|
static int ehci_fsl_init(int index, struct usb_ehci *ehci,
|
|
|
|
struct ehci_hccr *hccr, struct ehci_hcor *hcor)
|
2016-07-01 22:21:46 +09:00
|
|
|
#endif
|
2016-07-01 22:21:45 +09:00
|
|
|
{
|
2011-03-23 18:50:43 +09:00
|
|
|
const char *phy_type = NULL;
|
2018-11-21 16:43:56 +09:00
|
|
|
#if !CONFIG_IS_ENABLED(DM_USB)
|
2011-03-23 18:50:43 +09:00
|
|
|
size_t len;
|
2013-12-19 14:38:46 +09:00
|
|
|
char current_usb_controller[5];
|
2016-07-01 22:21:46 +09:00
|
|
|
#endif
|
2011-11-10 01:04:15 +09:00
|
|
|
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
|
|
|
char usb_phy[5];
|
2011-03-23 18:50:43 +09:00
|
|
|
|
|
|
|
usb_phy[0] = '\0';
|
2011-11-10 01:04:15 +09:00
|
|
|
#endif
|
2014-02-26 21:13:15 +09:00
|
|
|
if (has_erratum_a007075()) {
|
|
|
|
/*
|
|
|
|
* A 5ms delay is needed after applying soft-reset to the
|
|
|
|
* controller to let external ULPI phy come out of reset.
|
|
|
|
* This delay needs to be added before re-initializing
|
|
|
|
* the controller after soft-resetting completes
|
|
|
|
*/
|
|
|
|
mdelay(5);
|
|
|
|
}
|
2008-11-28 21:22:09 +09:00
|
|
|
|
|
|
|
/* Set to Host mode */
|
2009-06-19 21:26:00 +09:00
|
|
|
setbits_le32(&ehci->usbmode, CM_HOST);
|
2008-11-28 21:22:09 +09:00
|
|
|
|
2009-06-19 21:26:00 +09:00
|
|
|
out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
|
|
|
|
out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
|
2008-11-28 21:22:09 +09:00
|
|
|
|
|
|
|
/* Init phy */
|
2018-11-21 16:43:56 +09:00
|
|
|
#if CONFIG_IS_ENABLED(DM_USB)
|
2016-07-01 22:21:46 +09:00
|
|
|
if (priv->phy_type)
|
|
|
|
phy_type = priv->phy_type;
|
|
|
|
#else
|
|
|
|
memset(current_usb_controller, '\0', 5);
|
|
|
|
snprintf(current_usb_controller, sizeof(current_usb_controller),
|
|
|
|
"usb%d", index+1);
|
|
|
|
|
2013-12-19 14:38:46 +09:00
|
|
|
if (hwconfig_sub(current_usb_controller, "phy_type"))
|
|
|
|
phy_type = hwconfig_subarg(current_usb_controller,
|
|
|
|
"phy_type", &len);
|
2016-07-01 22:21:46 +09:00
|
|
|
#endif
|
2009-05-25 20:53:16 +09:00
|
|
|
else
|
2017-08-04 03:22:12 +09:00
|
|
|
phy_type = env_get("usb_phy_type");
|
2011-03-23 18:50:43 +09:00
|
|
|
|
|
|
|
if (!phy_type) {
|
|
|
|
#ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
|
|
|
/* if none specified assume internal UTMI */
|
|
|
|
strcpy(usb_phy, "utmi");
|
|
|
|
phy_type = usb_phy;
|
|
|
|
#else
|
|
|
|
printf("WARNING: USB phy type not defined !!\n");
|
|
|
|
return -1;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2014-02-17 20:28:36 +09:00
|
|
|
if (!strncmp(phy_type, "utmi", 4)) {
|
2011-03-23 18:50:43 +09:00
|
|
|
#if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
|
2014-05-08 20:35:26 +09:00
|
|
|
clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
|
|
|
|
PHY_CLK_SEL_UTMI);
|
|
|
|
clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
|
|
|
|
UTMI_PHY_EN);
|
2011-03-23 18:50:43 +09:00
|
|
|
udelay(1000); /* delay required for PHY Clk to appear */
|
|
|
|
#endif
|
2016-07-01 22:21:45 +09:00
|
|
|
out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
|
2014-05-08 20:35:26 +09:00
|
|
|
clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
|
|
|
|
USB_EN);
|
2011-03-23 18:50:43 +09:00
|
|
|
} else {
|
2014-05-08 20:35:26 +09:00
|
|
|
clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
|
|
|
|
PHY_CLK_SEL_ULPI);
|
|
|
|
clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
|
|
|
|
CONTROL_REGISTER_W1C_MASK, USB_EN);
|
2011-03-23 18:50:43 +09:00
|
|
|
udelay(1000); /* delay required for PHY Clk to appear */
|
2012-10-22 14:18:24 +09:00
|
|
|
if (!usb_phy_clk_valid(ehci))
|
|
|
|
return -EINVAL;
|
2016-07-01 22:21:45 +09:00
|
|
|
out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
|
2011-03-23 18:50:43 +09:00
|
|
|
}
|
2008-11-28 21:22:09 +09:00
|
|
|
|
2009-06-19 21:26:00 +09:00
|
|
|
out_be32(&ehci->prictrl, 0x0000000c);
|
|
|
|
out_be32(&ehci->age_cnt_limit, 0x00000040);
|
|
|
|
out_be32(&ehci->sictrl, 0x00000001);
|
2008-11-28 21:22:09 +09:00
|
|
|
|
2009-06-19 21:26:00 +09:00
|
|
|
in_le32(&ehci->usbmode);
|
2008-11-28 21:22:09 +09:00
|
|
|
|
2014-10-17 12:42:07 +09:00
|
|
|
if (has_erratum_a007798())
|
2014-04-07 12:16:14 +09:00
|
|
|
set_txfifothresh(ehci, TXFIFOTHRESH);
|
|
|
|
|
2014-11-21 20:55:21 +09:00
|
|
|
if (has_erratum_a004477()) {
|
|
|
|
/*
|
|
|
|
* When reset is issued while any ULPI transaction is ongoing
|
|
|
|
* then it may result to corruption of ULPI Function Control
|
|
|
|
* Register which eventually causes phy clock to enter low
|
|
|
|
* power mode which stops the clock. Thus delay is required
|
|
|
|
* before reset to let ongoing ULPI transaction complete.
|
|
|
|
*/
|
|
|
|
udelay(1);
|
|
|
|
}
|
2008-11-28 21:22:09 +09:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-04-07 12:16:14 +09:00
|
|
|
/*
|
|
|
|
* Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
|
|
|
|
* to counter DDR latencies in writing data into Tx buffer.
|
|
|
|
* This prevents Tx buffer from getting underrun
|
|
|
|
*/
|
|
|
|
static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
|
|
|
|
{
|
|
|
|
u32 cmd;
|
|
|
|
cmd = ehci_readl(&ehci->txfilltuning);
|
|
|
|
cmd &= ~TXFIFO_THRESH_MASK;
|
|
|
|
cmd |= TXFIFO_THRESH(txfifo_thresh);
|
|
|
|
ehci_writel(&ehci->txfilltuning, cmd);
|
|
|
|
}
|