2014-12-19 20:20:53 +09:00
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/*
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2016-07-19 21:56:13 +09:00
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* Copyright (C) 2014 Panasonic Corporation
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* Copyright (C) 2015-2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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2014-12-19 20:20:53 +09:00
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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2015-05-29 17:30:00 +09:00
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#include <linux/io.h>
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2016-03-18 16:41:45 +09:00
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#include <linux/sizes.h>
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2016-01-09 01:51:13 +09:00
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2016-03-18 16:41:45 +09:00
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#include "../soc-info.h"
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2016-01-09 01:51:13 +09:00
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#include "ddrphy-regs.h"
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2014-12-19 20:20:53 +09:00
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/* Select either decimal or hexadecimal */
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#if 1
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#define PRINTF_FORMAT "%2d"
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#else
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#define PRINTF_FORMAT "%02x"
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#endif
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/* field separator */
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#define FS " "
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2016-10-27 23:47:08 +09:00
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struct phy_param {
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resource_size_t base;
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unsigned int nr_dx;
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2016-03-18 16:41:45 +09:00
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};
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2016-10-27 23:47:08 +09:00
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static const struct phy_param uniphier_ld4_phy_param[] = {
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{ .base = 0x5bc01000, .nr_dx = 2, },
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{ .base = 0x5be01000, .nr_dx = 2, },
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{ /* sentinel */ }
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2016-03-18 16:41:45 +09:00
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};
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2016-10-27 23:47:08 +09:00
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static const struct phy_param uniphier_pro4_phy_param[] = {
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{ .base = 0x5bc01000, .nr_dx = 2, },
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{ .base = 0x5bc02000, .nr_dx = 2, },
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{ .base = 0x5be01000, .nr_dx = 2, },
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{ .base = 0x5be02000, .nr_dx = 2, },
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{ /* sentinel */ }
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};
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static const struct phy_param uniphier_sld8_phy_param[] = {
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{ .base = 0x5bc01000, .nr_dx = 2, },
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{ .base = 0x5be01000, .nr_dx = 2, },
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{ /* sentinel */ }
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2016-03-18 16:41:45 +09:00
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};
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2016-10-27 23:47:07 +09:00
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static void print_bdl(void __iomem *reg, int n)
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2014-12-19 20:20:53 +09:00
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{
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2016-10-27 23:47:07 +09:00
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u32 val = readl(reg);
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int i;
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for (i = 0; i < n; i++)
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printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
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2014-12-19 20:20:53 +09:00
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}
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2016-10-27 23:47:08 +09:00
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static void dump_loop(const struct phy_param *phy_param,
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2016-10-27 23:47:07 +09:00
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void (*callback)(void __iomem *))
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2014-12-19 20:20:53 +09:00
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{
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2016-10-27 23:47:07 +09:00
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void __iomem *phy_base, *dx_base;
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2016-03-18 16:41:45 +09:00
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int p, dx;
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2014-12-19 20:20:53 +09:00
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2016-10-27 23:47:08 +09:00
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for (p = 0; phy_param->base; phy_param++, p++) {
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phy_base = ioremap(phy_param->base, SZ_4K);
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2016-10-27 23:47:07 +09:00
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dx_base = phy_base + PHY_DX_BASE;
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2014-12-19 20:20:53 +09:00
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2016-10-27 23:47:08 +09:00
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for (dx = 0; dx < phy_param->nr_dx; dx++) {
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2016-03-18 16:41:45 +09:00
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printf("PHY%dDX%d:", p, dx);
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2016-10-27 23:47:07 +09:00
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(*callback)(dx_base);
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dx_base += PHY_DX_STRIDE;
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2016-03-18 16:41:45 +09:00
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printf("\n");
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2014-12-19 20:20:53 +09:00
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}
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2016-03-18 16:41:45 +09:00
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2016-10-27 23:47:07 +09:00
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iounmap(phy_base);
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2014-12-19 20:20:53 +09:00
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}
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}
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2016-10-27 23:47:07 +09:00
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static void __wbdl_dump(void __iomem *dx_base)
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2014-12-19 20:20:53 +09:00
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{
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2016-10-27 23:47:07 +09:00
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print_bdl(dx_base + PHY_DX_BDLR0, 5);
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print_bdl(dx_base + PHY_DX_BDLR1, 5);
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2014-12-19 20:20:53 +09:00
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2016-10-27 23:47:07 +09:00
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printf(FS "(+" PRINTF_FORMAT ")",
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readl(dx_base + PHY_DX_LCDLR1) & 0xff);
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2014-12-19 20:20:53 +09:00
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}
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2016-10-27 23:47:08 +09:00
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static void wbdl_dump(const struct phy_param *phy_param)
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2014-12-19 20:20:53 +09:00
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{
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printf("\n--- Write Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
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2016-10-27 23:47:08 +09:00
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dump_loop(phy_param, &__wbdl_dump);
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2014-12-19 20:20:53 +09:00
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}
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2016-10-27 23:47:07 +09:00
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static void __rbdl_dump(void __iomem *dx_base)
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2014-12-19 20:20:53 +09:00
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{
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2016-10-27 23:47:07 +09:00
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print_bdl(dx_base + PHY_DX_BDLR3, 5);
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print_bdl(dx_base + PHY_DX_BDLR4, 4);
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2014-12-19 20:20:53 +09:00
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2016-10-27 23:47:07 +09:00
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printf(FS "(+" PRINTF_FORMAT ")",
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(readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
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2014-12-19 20:20:53 +09:00
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}
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2016-10-27 23:47:08 +09:00
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static void rbdl_dump(const struct phy_param *phy_param)
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2014-12-19 20:20:53 +09:00
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{
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printf("\n--- Read Bit Delay Line ---\n");
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printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
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2016-10-27 23:47:08 +09:00
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dump_loop(phy_param, &__rbdl_dump);
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2014-12-19 20:20:53 +09:00
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}
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2016-10-27 23:47:07 +09:00
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static void __wld_dump(void __iomem *dx_base)
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2014-12-19 20:20:53 +09:00
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{
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int rank;
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2016-10-27 23:47:07 +09:00
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u32 lcdlr0 = readl(dx_base + PHY_DX_LCDLR0);
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u32 gtr = readl(dx_base + PHY_DX_GTR);
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2014-12-19 20:20:53 +09:00
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for (rank = 0; rank < 4; rank++) {
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u32 wld = (lcdlr0 >> (8 * rank)) & 0xff; /* Delay */
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u32 wlsl = (gtr >> (12 + 2 * rank)) & 0x3; /* System Latency */
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printf(FS PRINTF_FORMAT "%sT", wld,
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wlsl == 0 ? "-1" : wlsl == 1 ? "+0" : "+1");
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}
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}
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2016-10-27 23:47:08 +09:00
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static void wld_dump(const struct phy_param *phy_param)
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2014-12-19 20:20:53 +09:00
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{
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printf("\n--- Write Leveling Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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2016-10-27 23:47:08 +09:00
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dump_loop(phy_param, &__wld_dump);
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2014-12-19 20:20:53 +09:00
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}
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2016-10-27 23:47:07 +09:00
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static void __dqsgd_dump(void __iomem *dx_base)
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2014-12-19 20:20:53 +09:00
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{
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int rank;
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2016-10-27 23:47:07 +09:00
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u32 lcdlr2 = readl(dx_base + PHY_DX_LCDLR2);
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u32 gtr = readl(dx_base + PHY_DX_GTR);
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2014-12-19 20:20:53 +09:00
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for (rank = 0; rank < 4; rank++) {
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u32 dqsgd = (lcdlr2 >> (8 * rank)) & 0xff; /* Delay */
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u32 dgsl = (gtr >> (3 * rank)) & 0x7; /* System Latency */
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printf(FS PRINTF_FORMAT "+%dT", dqsgd, dgsl);
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}
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}
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2016-10-27 23:47:08 +09:00
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static void dqsgd_dump(const struct phy_param *phy_param)
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2014-12-19 20:20:53 +09:00
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{
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printf("\n--- DQS Gating Delay ---\n");
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printf(" Rank0 Rank1 Rank2 Rank3\n");
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2016-10-27 23:47:08 +09:00
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dump_loop(phy_param, &__dqsgd_dump);
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2014-12-19 20:20:53 +09:00
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}
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2016-10-27 23:47:07 +09:00
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static void __mdl_dump(void __iomem *dx_base)
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2014-12-19 20:20:53 +09:00
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{
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int i;
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2016-10-27 23:47:07 +09:00
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u32 mdl = readl(dx_base + PHY_DX_MDLR);
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2014-12-19 20:20:53 +09:00
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for (i = 0; i < 3; i++)
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printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
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}
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2016-10-27 23:47:08 +09:00
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static void mdl_dump(const struct phy_param *phy_param)
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2014-12-19 20:20:53 +09:00
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{
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printf("\n--- Master Delay Line ---\n");
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printf(" IPRD TPRD MDLD\n");
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2016-10-27 23:47:08 +09:00
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dump_loop(phy_param, &__mdl_dump);
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2014-12-19 20:20:53 +09:00
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}
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2016-10-27 23:47:07 +09:00
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#define REG_DUMP(x) \
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{ int ofst = PHY_ ## x; void __iomem *reg = phy_base + ofst; \
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printf("%3d: %-10s: %p : %08x\n", \
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ofst >> PHY_REG_SHIFT, #x, reg, readl(reg)); }
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#define DX_REG_DUMP(dx, x) \
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{ int ofst = PHY_DX_BASE + PHY_DX_STRIDE * (dx) + \
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PHY_DX_## x; \
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void __iomem *reg = phy_base + ofst; \
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printf("%3d: DX%d%-7s: %p : %08x\n", \
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ofst >> PHY_REG_SHIFT, (dx), #x, reg, readl(reg)); }
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2014-12-19 20:20:53 +09:00
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2016-10-27 23:47:08 +09:00
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static void reg_dump(const struct phy_param *phy_param)
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2014-12-19 20:20:53 +09:00
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{
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2016-10-27 23:47:07 +09:00
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void __iomem *phy_base;
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int p, dx;
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2014-12-19 20:20:53 +09:00
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printf("\n--- DDR PHY registers ---\n");
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2016-10-27 23:47:08 +09:00
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for (p = 0; phy_param->base; phy_param++, p++) {
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phy_base = ioremap(phy_param->base, SZ_4K);
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2016-03-18 16:41:45 +09:00
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2016-10-27 23:47:07 +09:00
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printf("== PHY%d (base: %p) ==\n", p, phy_base);
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2016-03-18 16:41:45 +09:00
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printf(" No: Name : Address : Data\n");
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2016-10-27 23:47:07 +09:00
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REG_DUMP(RIDR);
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REG_DUMP(PIR);
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REG_DUMP(PGCR0);
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REG_DUMP(PGCR1);
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REG_DUMP(PGSR0);
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REG_DUMP(PGSR1);
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REG_DUMP(PLLCR);
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REG_DUMP(PTR0);
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REG_DUMP(PTR1);
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REG_DUMP(PTR2);
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REG_DUMP(PTR3);
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REG_DUMP(PTR4);
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REG_DUMP(ACMDLR);
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REG_DUMP(ACBDLR);
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REG_DUMP(DXCCR);
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REG_DUMP(DSGCR);
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REG_DUMP(DCR);
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REG_DUMP(DTPR0);
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REG_DUMP(DTPR1);
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REG_DUMP(DTPR2);
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REG_DUMP(MR0);
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REG_DUMP(MR1);
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REG_DUMP(MR2);
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REG_DUMP(MR3);
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2016-10-27 23:47:08 +09:00
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for (dx = 0; dx < phy_param->nr_dx; dx++) {
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2016-10-27 23:47:07 +09:00
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DX_REG_DUMP(dx, GCR);
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DX_REG_DUMP(dx, GTR);
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}
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iounmap(phy_base);
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2014-12-19 20:20:53 +09:00
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}
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}
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static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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char *cmd = argv[1];
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2016-10-27 23:47:08 +09:00
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const struct phy_param *phy_param;
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2016-03-18 16:41:45 +09:00
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switch (uniphier_get_soc_type()) {
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case SOC_UNIPHIER_LD4:
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2016-10-27 23:47:08 +09:00
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phy_param = uniphier_ld4_phy_param;
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2016-03-18 16:41:45 +09:00
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break;
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case SOC_UNIPHIER_PRO4:
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2016-10-27 23:47:08 +09:00
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phy_param = uniphier_pro4_phy_param;
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2016-03-18 16:41:45 +09:00
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break;
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case SOC_UNIPHIER_SLD8:
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2016-10-27 23:47:08 +09:00
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phy_param = uniphier_sld8_phy_param;
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2016-03-18 16:41:45 +09:00
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break;
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default:
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printf("unsupported SoC\n");
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return CMD_RET_FAILURE;
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}
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2014-12-19 20:20:53 +09:00
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if (argc == 1)
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cmd = "all";
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if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
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2016-10-27 23:47:08 +09:00
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wbdl_dump(phy_param);
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2014-12-19 20:20:53 +09:00
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if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
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2016-10-27 23:47:08 +09:00
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rbdl_dump(phy_param);
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2014-12-19 20:20:53 +09:00
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if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
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2016-10-27 23:47:08 +09:00
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wld_dump(phy_param);
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2014-12-19 20:20:53 +09:00
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if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
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2016-10-27 23:47:08 +09:00
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dqsgd_dump(phy_param);
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2014-12-19 20:20:53 +09:00
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if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
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2016-10-27 23:47:08 +09:00
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mdl_dump(phy_param);
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2014-12-19 20:20:53 +09:00
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if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
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2016-10-27 23:47:08 +09:00
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reg_dump(phy_param);
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2014-12-19 20:20:53 +09:00
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2016-03-18 16:41:45 +09:00
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return CMD_RET_SUCCESS;
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2014-12-19 20:20:53 +09:00
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}
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U_BOOT_CMD(
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ddr, 2, 1, do_ddr,
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"UniPhier DDR PHY parameters dumper",
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2016-08-21 16:12:36 +09:00
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"- dump all of the following\n"
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2014-12-19 20:20:53 +09:00
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"ddr wbdl - dump Write Bit Delay\n"
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"ddr rbdl - dump Read Bit Delay\n"
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"ddr wld - dump Write Leveling\n"
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"ddr dqsgd - dump DQS Gating Delay\n"
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"ddr mdl - dump Master Delay Line\n"
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"ddr reg - dump registers\n"
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);
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