mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 00:18:51 +09:00
452 lines
11 KiB
C
452 lines
11 KiB
C
![]() |
/*
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* (C) Copyright 2001
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* Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <command.h>
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#include <cmd_boot.h>
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#include <malloc.h>
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/* ------------------------------------------------------------------------- */
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#if 0
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#define FPGA_DEBUG
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#endif
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/* fpga configuration data - generated by bin2cc */
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const unsigned char fpgadata[] =
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{
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#ifdef CONFIG_CPCI405_VER2
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# include "fpgadata_cpci4052.c"
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#else
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# include "fpgadata_cpci405.c"
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#endif
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};
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/*
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* include common fpga code (for esd boards)
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*/
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#include "../common/fpga.c"
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/* Prototypes */
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int version2(void);
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int gunzip(void *, int, unsigned char *, int *);
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int board_pre_init (void)
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{
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#ifndef CONFIG_CPCI405_VER2
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int index, len, i;
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int status;
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#endif
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#ifdef FPGA_DEBUG
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DECLARE_GLOBAL_DATA_PTR;
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f();
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#endif
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/*
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* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
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*/
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out32(IBM405GP_GPIO0_ODR, 0x00000000); /* no open drain pins */
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out32(IBM405GP_GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
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out32(IBM405GP_GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
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out32(IBM405GP_GPIO0_OR, 0); /* pull prg low */
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/*
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* Boot onboard FPGA
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*/
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#ifndef CONFIG_CPCI405_VER2
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if (!version2()) {
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status = fpga_boot((unsigned char *)fpgadata, sizeof(fpgadata));
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if (status != 0) {
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/* booting FPGA failed */
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#ifndef FPGA_DEBUG
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DECLARE_GLOBAL_DATA_PTR;
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/* set up serial port with default baudrate */
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(void) get_clocks ();
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gd->baudrate = CONFIG_BAUDRATE;
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serial_init ();
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console_init_f();
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#endif
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = fpgadata[index];
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printf("FPGA: %s\n", &(fpgadata[index+1]));
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index += len+3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i=20; i>0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index=0;index<1000;index++)
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udelay(1000);
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}
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putc ('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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}
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#endif /* !CONFIG_CPCI405_VER2 */
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/*
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* IRQ 0-15 405GP internally generated; active high; level sensitive
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* IRQ 16 405GP internally generated; active low; level sensitive
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* IRQ 17-24 RESERVED
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* IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
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* IRQ 26 (EXT IRQ 1) CAN1 (+FPGA on CPCI4052) ; active low; level sensitive
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* IRQ 27 (EXT IRQ 2) PCI SLOT 0; active low; level sensitive
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* IRQ 28 (EXT IRQ 3) PCI SLOT 1; active low; level sensitive
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* IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
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* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
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* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
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*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
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mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
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mtdcr(uictr, 0x10000000); /* set int trigger levels */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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int ctermm2(void)
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{
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#ifdef CONFIG_CPCI405_VER2
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return 0; /* no, board is cpci405 */
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#else
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if ((*(unsigned char *)0xf0000400 == 0x00) &&
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(*(unsigned char *)0xf0000401 == 0x01))
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return 0; /* no, board is cpci405 */
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else
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return -1; /* yes, board is cterm-m2 */
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#endif
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}
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int cpci405_host(void)
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{
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if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
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return -1; /* yes, board is cpci405 host */
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else
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return 0; /* no, board is cpci405 adapter */
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}
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int version2(void)
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{
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unsigned long cntrl0Reg;
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unsigned long value;
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/*
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* Setup GPIO pins (CS2/GPIO11 as GPIO)
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*/
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg | 0x02000000);
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udelay(1000); /* wait some time before reading input */
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value = in32(IBM405GP_GPIO0_IR) & 0x00100000; /* test GPIO11 */
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/*
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* Setup GPIO pins (CS2/GPIO11 as CS again)
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*/
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mtdcr(cntrl0, cntrl0Reg);
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if (value)
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return 0; /* no, board is version 1.x */
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else
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return -1; /* yes, board is version 2.x */
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}
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int misc_init_f (void)
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{
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return 0; /* dummy implementation */
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}
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int misc_init_r (void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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bd_t *bd = gd->bd;
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char * tmp; /* Temporary char pointer */
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#ifdef CONFIG_CPCI405_VER2
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unsigned char *dst;
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ulong len = sizeof(fpgadata);
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int status;
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int index;
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int i;
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unsigned long cntrl0Reg;
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/*
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* On CPCI-405 version 2 the environment is saved in eeprom!
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* FPGA can be gzip compressed (malloc) and booted this late.
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*/
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if (version2()) {
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/*
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* Setup GPIO pins (CS6+CS7 as GPIO)
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*/
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cntrl0Reg = mfdcr(cntrl0);
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mtdcr(cntrl0, cntrl0Reg | 0x00300000);
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dst = malloc(CFG_FPGA_MAX_SIZE);
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if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, (int *)&len) != 0) {
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printf ("GUNZIP ERROR - must RESET board to recover\n");
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do_reset (NULL, 0, 0, NULL);
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}
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status = fpga_boot(dst, len);
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if (status != 0) {
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printf("\nFPGA: Booting failed ");
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switch (status) {
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case ERROR_FPGA_PRG_INIT_LOW:
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printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_INIT_HIGH:
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printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
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break;
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case ERROR_FPGA_PRG_DONE:
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printf("(Timeout: DONE not high after programming FPGA)\n ");
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break;
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}
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("FPGA: %s\n", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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/* delayed reboot */
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for (i=20; i>0; i--) {
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printf("Rebooting in %2d seconds \r",i);
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for (index=0;index<1000;index++)
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udelay(1000);
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}
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putc ('\n');
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do_reset(NULL, 0, 0, NULL);
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}
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/* restore gpio/cs settings */
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mtdcr(cntrl0, cntrl0Reg);
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puts("FPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = dst[index];
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printf("%s ", &(dst[index+1]));
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index += len+3;
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}
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putc ('\n');
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free(dst);
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}
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else {
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printf("\n*** U-Boot Version does not match Board Version!\n");
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printf("*** CPCI-405 Version 2.x detected!\n");
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printf("*** Please use correct U-Boot version (CPCI4052)!\n\n");
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}
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#else /* CONFIG_CPCI405_VER2 */
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/*
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* Generate last byte of ip-addr from code-plug @ 0xf0000400
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*/
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if (ctermm2()) {
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char str[32];
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unsigned char ipbyte = *(unsigned char *)0xf0000400;
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/*
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* Only overwrite ip-addr with allowed values
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*/
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if ((ipbyte != 0x00) && (ipbyte != 0xff)) {
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bd->bi_ip_addr = (bd->bi_ip_addr & 0xffffff00) | ipbyte;
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sprintf(str, "%ld.%ld.%ld.%ld",
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(bd->bi_ip_addr & 0xff000000) >> 24,
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(bd->bi_ip_addr & 0x00ff0000) >> 16,
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(bd->bi_ip_addr & 0x0000ff00) >> 8,
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(bd->bi_ip_addr & 0x000000ff));
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setenv("ipaddr", str);
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}
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}
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if (version2()) {
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printf("\n*** U-Boot Version does not match Board Version!\n");
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printf("*** CPCI-405 Board Version 1.x detected!\n");
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printf("*** Please use correct U-Boot version (CPCI405)!\n\n");
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}
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#endif /* CONFIG_CPCI405_VER2 */
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/*
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* Write ethernet addr in NVRAM for VxWorks
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*/
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tmp = (char *)CFG_NVRAM_BASE_ADDR + CFG_NVRAM_VXWORKS_OFFS;
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memcpy( (char *)tmp, (char *)&bd->bi_enetaddr[0], 6 );
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return (0);
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}
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/*
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* Check Board Identity:
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*/
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int checkboard (void)
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{
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#ifndef CONFIG_CPCI405_VER2
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int index;
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int len;
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#endif
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unsigned char str[64];
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int i = getenv_r ("serial#", str, sizeof(str));
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puts ("Board: ");
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if (i == -1) {
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puts ("### No HW ID - assuming CPCI405");
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} else {
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puts(str);
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}
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if (version2())
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puts (" (Ver 2.x, ");
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else
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puts (" (Ver 1.x, ");
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#if 0
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if ((*(unsigned short *)((unsigned long)CFG_FPGA_BASE_ADDR) + CFG_FPGA_STATUS)
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& CFG_FPGA_STATUS_FLASH)
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puts ("FLASH Bank A, ");
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else
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puts ("FLASH Bank B, ");
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#endif
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if (ctermm2()) {
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printf("CTERM-M2 - Id=0x%02x)", *(unsigned char *)0xf0000400);
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} else {
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if (cpci405_host()) {
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puts ("PCI Host Version)");
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} else {
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puts ("PCI Adapter Version)");
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}
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}
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#ifndef CONFIG_CPCI405_VER2
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puts ("\nFPGA: ");
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/* display infos on fpgaimage */
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index = 15;
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for (i=0; i<4; i++) {
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len = fpgadata[index];
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printf("%s ", &(fpgadata[index+1]));
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index += len+3;
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}
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#endif
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putc ('\n');
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return 0;
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}
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/* ------------------------------------------------------------------------- */
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long int initdram (int board_type)
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{
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unsigned long val;
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mtdcr(memcfga, mem_mb0cf);
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val = mfdcr(memcfgd);
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#if 0
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printf("\nmb0cf=%x\n", val); /* test-only */
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printf("strap=%x\n", mfdcr(strap)); /* test-only */
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#endif
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return (4*1024*1024 << ((val & 0x000e0000) >> 17));
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}
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/* ------------------------------------------------------------------------- */
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int testdram (void)
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{
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/* TODO: XXX XXX XXX */
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printf ("test: 16 MB - ok\n");
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return (0);
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}
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/* ------------------------------------------------------------------------- */
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#ifdef CONFIG_CPCI405_VER2
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#ifdef CONFIG_IDE_RESET
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void ide_set_reset(int on)
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{
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volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
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/*
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* Assert or deassert CompactFlash Reset Pin
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*/
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if (on) { /* assert RESET */
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*fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
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} else { /* release RESET */
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*fpga_mode |= CFG_FPGA_MODE_CF_RESET;
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}
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}
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#endif /* CONFIG_IDE_RESET */
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#endif /* CONFIG_CPCI405_VER2 */
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/* ------------------------------------------------------------------------- */
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