2010-10-21 17:50:05 +09:00
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/*
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* (C) Copyright 2010
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* Dirk Eibach, Guntermann & Drunck GmbH, eibach@gdsys.de
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*
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2013-07-08 16:37:19 +09:00
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* SPDX-License-Identifier: GPL-2.0+
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2010-10-21 17:50:05 +09:00
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/ppc4xx-gpio.h>
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2012-04-26 12:54:22 +09:00
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#include "405ep.h"
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2011-01-21 17:31:21 +09:00
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#include <gdsys_fpga.h>
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2010-10-21 17:50:05 +09:00
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2011-01-21 17:31:21 +09:00
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#include "../common/osd.h"
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2010-10-21 17:50:05 +09:00
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2012-04-26 12:54:22 +09:00
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#define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
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#define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
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#define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
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2010-10-21 17:50:05 +09:00
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enum {
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UNITTYPE_MAIN_SERVER = 0,
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UNITTYPE_MAIN_USER = 1,
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UNITTYPE_VIDEO_SERVER = 2,
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UNITTYPE_VIDEO_USER = 3,
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};
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enum {
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HWVER_100 = 0,
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HWVER_104 = 1,
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HWVER_110 = 2,
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};
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enum {
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COMPRESSION_NONE = 0,
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COMPRESSION_TYPE1_DELTA,
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};
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enum {
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AUDIO_NONE = 0,
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AUDIO_TX = 1,
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AUDIO_RX = 2,
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AUDIO_RXTX = 3,
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};
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enum {
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SYSCLK_147456 = 0,
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};
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enum {
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RAM_DDR2_32 = 0,
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};
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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2012-04-26 12:54:23 +09:00
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char *s = getenv("serial#");
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puts("Board: ");
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puts("IoCon");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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puts("\n");
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return 0;
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}
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static void print_fpga_info(void)
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{
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2012-04-27 17:33:46 +09:00
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struct ihs_fpga *fpga = (struct ihs_fpga *) CONFIG_SYS_FPGA_BASE(0);
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2011-01-21 17:31:21 +09:00
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u16 versions = in_le16(&fpga->versions);
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u16 fpga_version = in_le16(&fpga->fpga_version);
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u16 fpga_features = in_le16(&fpga->fpga_features);
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2010-10-21 17:50:05 +09:00
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unsigned unit_type;
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unsigned hardware_version;
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unsigned feature_compression;
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unsigned feature_osd;
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unsigned feature_audio;
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unsigned feature_sysclock;
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unsigned feature_ramconfig;
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unsigned feature_carriers;
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unsigned feature_video_channels;
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unit_type = (versions & 0xf000) >> 12;
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hardware_version = versions & 0x000f;
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feature_compression = (fpga_features & 0xe000) >> 13;
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feature_osd = fpga_features & (1<<11);
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feature_audio = (fpga_features & 0x0600) >> 9;
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feature_sysclock = (fpga_features & 0x0180) >> 7;
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feature_ramconfig = (fpga_features & 0x0060) >> 5;
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feature_carriers = (fpga_features & 0x000c) >> 2;
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feature_video_channels = fpga_features & 0x0003;
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switch (unit_type) {
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case UNITTYPE_MAIN_USER:
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printf("Mainchannel");
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break;
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case UNITTYPE_VIDEO_USER:
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printf("Videochannel");
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break;
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default:
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printf("UnitType %d(not supported)", unit_type);
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break;
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}
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switch (hardware_version) {
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case HWVER_100:
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printf(" HW-Ver 1.00\n");
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break;
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case HWVER_104:
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printf(" HW-Ver 1.04\n");
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break;
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case HWVER_110:
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printf(" HW-Ver 1.10\n");
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break;
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default:
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printf(" HW-Ver %d(not supported)\n",
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hardware_version);
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break;
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}
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printf(" FPGA V %d.%02d, features:",
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fpga_version / 100, fpga_version % 100);
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switch (feature_compression) {
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case COMPRESSION_NONE:
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printf(" no compression");
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break;
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case COMPRESSION_TYPE1_DELTA:
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printf(" type1-deltacompression");
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break;
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default:
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printf(" compression %d(not supported)", feature_compression);
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break;
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}
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printf(", %sosd", feature_osd ? "" : "no ");
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switch (feature_audio) {
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case AUDIO_NONE:
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printf(", no audio");
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break;
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case AUDIO_TX:
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printf(", audio tx");
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break;
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case AUDIO_RX:
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printf(", audio rx");
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break;
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case AUDIO_RXTX:
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printf(", audio rx+tx");
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break;
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default:
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printf(", audio %d(not supported)", feature_audio);
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break;
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}
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puts(",\n ");
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switch (feature_sysclock) {
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case SYSCLK_147456:
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printf("clock 147.456 MHz");
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break;
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default:
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printf("clock %d(not supported)", feature_sysclock);
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break;
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}
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switch (feature_ramconfig) {
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case RAM_DDR2_32:
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printf(", RAM 32 bit DDR2");
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break;
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default:
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printf(", RAM %d(not supported)", feature_ramconfig);
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break;
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}
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printf(", %d carrier(s)", feature_carriers);
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printf(", %d video channel(s)\n", feature_video_channels);
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}
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int last_stage_init(void)
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{
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2012-04-26 12:54:23 +09:00
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print_fpga_info();
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2011-01-21 17:31:21 +09:00
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return osd_probe(0);
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2010-10-21 17:50:05 +09:00
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}
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/*
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* provide access to fpga gpios (for I2C bitbang)
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*/
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void fpga_gpio_set(int pin)
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{
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2011-01-21 17:31:21 +09:00
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out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x18), pin);
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2010-10-21 17:50:05 +09:00
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}
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void fpga_gpio_clear(int pin)
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{
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2011-01-21 17:31:21 +09:00
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out_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x16), pin);
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2010-10-21 17:50:05 +09:00
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}
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int fpga_gpio_get(int pin)
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{
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2011-01-21 17:31:21 +09:00
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return in_le16((void *)(CONFIG_SYS_FPGA0_BASE + 0x14)) & pin;
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2010-10-21 17:50:05 +09:00
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}
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2012-04-26 12:54:22 +09:00
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void gd405ep_init(void)
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{
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}
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void gd405ep_set_fpga_reset(unsigned state)
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{
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if (state) {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
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} else {
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out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
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out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
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}
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}
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void gd405ep_setup_hw(void)
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{
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/*
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* set "startup-finished"-gpios
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*/
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gpio_write_bit(21, 0);
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gpio_write_bit(22, 1);
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}
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int gd405ep_get_fpga_done(unsigned fpga)
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{
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return in_le16((void *)LATCH2_BASE) & CONFIG_SYS_FPGA_DONE(fpga);
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}
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