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https://github.com/brain-hackers/u-boot-brain
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826 lines
24 KiB
C
826 lines
24 KiB
C
![]() |
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Texas Instruments' AM654 DDRSS driver
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*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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* Lokesh Vutla <lokeshvutla@ti.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <ram.h>
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#include <asm/io.h>
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#include <power-domain.h>
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#include <dm.h>
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#include <asm/arch/sys_proto.h>
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#include <power/regulator.h>
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#include "k3-am654-ddrss.h"
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#define LDELAY 10000
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/* DDRSS PHY configuration register fixed values */
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#define DDRSS_DDRPHY_RANKIDR_RANK0 0
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/**
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* struct am654_ddrss_desc - Description of ddrss integration.
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* @dev: DDRSS device pointer
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* @ddrss_ss_cfg: DDRSS wrapper logic region base address
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* @ddrss_ctl_cfg: DDRSS controller region base address
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* @ddrss_phy_cfg: DDRSS PHY region base address
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* @ddrss_clk: DDRSS clock description
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* @vtt_supply: VTT Supply regulator
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* @ddrss_pwrdmn: DDRSS power domain description
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* @params: SDRAM configuration parameters
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*/
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struct am654_ddrss_desc {
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struct udevice *dev;
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void __iomem *ddrss_ss_cfg;
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void __iomem *ddrss_ctl_cfg;
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void __iomem *ddrss_phy_cfg;
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struct clk ddrss_clk;
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struct udevice *vtt_supply;
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struct power_domain ddrcfg_pwrdmn;
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struct power_domain ddrdata_pwrdmn;
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struct ddrss_params params;
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};
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static inline u32 ddrss_readl(void __iomem *addr, unsigned int offset)
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{
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return readl(addr + offset);
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}
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static inline void ddrss_writel(void __iomem *addr, unsigned int offset,
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u32 data)
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{
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debug("%s: addr = 0x%p, value = 0x%x\n", __func__, addr + offset, data);
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writel(data, addr + offset);
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}
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#define ddrss_ctl_writel(off, val) ddrss_writel(ddrss->ddrss_ctl_cfg, off, val)
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#define ddrss_ctl_readl(off) ddrss_readl(ddrss->ddrss_ctl_cfg, off)
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static inline u32 am654_ddrss_get_type(struct am654_ddrss_desc *ddrss)
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{
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return ddrss_ctl_readl(DDRSS_DDRCTL_MSTR) & MSTR_DDR_TYPE_MASK;
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}
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/**
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* am654_ddrss_dram_wait_for_init_complete() - Wait for init to complete
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*
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* After detecting the DDR type this function will pause until the
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* initialization is complete. Each DDR type has mask of multiple bits.
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* The size of the field depends on the DDR Type. If the initialization
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* does not complete and error will be returned and will cause the boot to halt.
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*
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*/
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static int am654_ddrss_dram_wait_for_init_complt(struct am654_ddrss_desc *ddrss)
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{
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u32 val, mask;
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val = am654_ddrss_get_type(ddrss);
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switch (val) {
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case DDR_TYPE_LPDDR4:
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case DDR_TYPE_DDR4:
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mask = DDR4_STAT_MODE_MASK;
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break;
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case DDR_TYPE_DDR3:
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mask = DDR3_STAT_MODE_MASK;
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break;
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default:
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printf("Unsupported DDR type 0x%x\n", val);
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return -EINVAL;
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}
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if (!wait_on_value(mask, DDR_MODE_NORMAL,
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ddrss->ddrss_ctl_cfg + DDRSS_DDRCTL_STAT, LDELAY))
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return -ETIMEDOUT;
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return 0;
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}
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/**
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* am654_ddrss_ctrl_configuration() - Configure Controller specific registers
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* @dev: corresponding ddrss device
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*/
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static void am654_ddrss_ctrl_configuration(struct am654_ddrss_desc *ddrss)
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{
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struct ddrss_ddrctl_timing_params *tmg = &ddrss->params.ctl_timing;
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struct ddrss_ddrctl_reg_params *reg = &ddrss->params.ctl_reg;
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struct ddrss_ddrctl_ecc_params *ecc = &ddrss->params.ctl_ecc;
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struct ddrss_ddrctl_crc_params *crc = &ddrss->params.ctl_crc;
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struct ddrss_ddrctl_map_params *map = &ddrss->params.ctl_map;
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u32 val;
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debug("%s: DDR controller register configuration started\n", __func__);
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ddrss_ctl_writel(DDRSS_DDRCTL_MSTR, reg->ddrctl_mstr);
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ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL0, reg->ddrctl_rfshctl0);
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ddrss_ctl_writel(DDRSS_DDRCTL_RFSHTMG, reg->ddrctl_rfshtmg);
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ddrss_ctl_writel(DDRSS_DDRCTL_ECCCFG0, ecc->ddrctl_ecccfg0);
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ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL0, crc->ddrctl_crcparctl0);
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ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL1, crc->ddrctl_crcparctl1);
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ddrss_ctl_writel(DDRSS_DDRCTL_CRCPARCTL2, crc->ddrctl_crcparctl2);
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ddrss_ctl_writel(DDRSS_DDRCTL_INIT0, reg->ddrctl_init0);
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ddrss_ctl_writel(DDRSS_DDRCTL_INIT1, reg->ddrctl_init1);
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ddrss_ctl_writel(DDRSS_DDRCTL_INIT3, reg->ddrctl_init3);
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ddrss_ctl_writel(DDRSS_DDRCTL_INIT4, reg->ddrctl_init4);
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ddrss_ctl_writel(DDRSS_DDRCTL_INIT5, reg->ddrctl_init5);
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ddrss_ctl_writel(DDRSS_DDRCTL_INIT6, reg->ddrctl_init6);
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ddrss_ctl_writel(DDRSS_DDRCTL_INIT7, reg->ddrctl_init7);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG0, tmg->ddrctl_dramtmg0);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG1, tmg->ddrctl_dramtmg1);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2, tmg->ddrctl_dramtmg2);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG3, tmg->ddrctl_dramtmg3);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG4, tmg->ddrctl_dramtmg4);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG5, tmg->ddrctl_dramtmg5);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG8, tmg->ddrctl_dramtmg8);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG9, tmg->ddrctl_dramtmg9);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG11, tmg->ddrctl_dramtmg11);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG12, tmg->ddrctl_dramtmg12);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG13, tmg->ddrctl_dramtmg13);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG15, tmg->ddrctl_dramtmg15);
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ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG17, tmg->ddrctl_dramtmg17);
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ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL0, reg->ddrctl_zqctl0);
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ddrss_ctl_writel(DDRSS_DDRCTL_ZQCTL1, reg->ddrctl_zqctl1);
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ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG0, reg->ddrctl_dfitmg0);
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ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG1, reg->ddrctl_dfitmg1);
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ddrss_ctl_writel(DDRSS_DDRCTL_DFITMG2, reg->ddrctl_dfitmg2);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP0, map->ddrctl_addrmap0);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP1, map->ddrctl_addrmap1);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP2, map->ddrctl_addrmap2);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP3, map->ddrctl_addrmap3);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP4, map->ddrctl_addrmap4);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP5, map->ddrctl_addrmap5);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP6, map->ddrctl_addrmap6);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP7, map->ddrctl_addrmap7);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP8, map->ddrctl_addrmap8);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP9, map->ddrctl_addrmap9);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP10, map->ddrctl_addrmap10);
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ddrss_ctl_writel(DDRSS_DDRCTL_ADDRMAP11, map->ddrctl_addrmap11);
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ddrss_ctl_writel(DDRSS_DDRCTL_ODTCFG, reg->ddrctl_odtcfg);
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ddrss_ctl_writel(DDRSS_DDRCTL_ODTMAP, reg->ddrctl_odtmap);
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/* Disable refreshes */
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val = ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3);
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val |= 0x01;
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ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3, val);
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debug("%s: DDR controller configuration completed\n", __func__);
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}
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#define ddrss_phy_writel(off, val) \
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do { \
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ddrss_writel(ddrss->ddrss_phy_cfg, off, val); \
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sdelay(10); /* Delay at least 20 clock cycles */ \
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} while (0)
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#define ddrss_phy_readl(off) \
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({ \
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u32 val = ddrss_readl(ddrss->ddrss_phy_cfg, off); \
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sdelay(10); /* Delay at least 20 clock cycles */ \
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val; \
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})
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/**
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* am654_ddrss_phy_configuration() - Configure PHY specific registers
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* @ddrss: corresponding ddrss device
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*/
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static void am654_ddrss_phy_configuration(struct am654_ddrss_desc *ddrss)
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{
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struct ddrss_ddrphy_ioctl_params *ioctl = &ddrss->params.phy_ioctl;
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struct ddrss_ddrphy_timing_params *tmg = &ddrss->params.phy_timing;
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struct ddrss_ddrphy_ctrl_params *ctrl = &ddrss->params.phy_ctrl;
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struct ddrss_ddrphy_cfg_params *cfg = &ddrss->params.phy_cfg;
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struct ddrss_ddrphy_zq_params *zq = &ddrss->params.phy_zq;
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debug("%s: DDR phy register configuration started\n", __func__);
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ddrss_phy_writel(DDRSS_DDRPHY_PGCR1, cfg->ddrphy_pgcr1);
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ddrss_phy_writel(DDRSS_DDRPHY_PGCR2, cfg->ddrphy_pgcr2);
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ddrss_phy_writel(DDRSS_DDRPHY_PGCR3, cfg->ddrphy_pgcr3);
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ddrss_phy_writel(DDRSS_DDRPHY_PGCR6, cfg->ddrphy_pgcr6);
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ddrss_phy_writel(DDRSS_DDRPHY_PTR3, tmg->ddrphy_ptr3);
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ddrss_phy_writel(DDRSS_DDRPHY_PTR4, tmg->ddrphy_ptr4);
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ddrss_phy_writel(DDRSS_DDRPHY_PTR5, tmg->ddrphy_ptr5);
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ddrss_phy_writel(DDRSS_DDRPHY_PTR6, tmg->ddrphy_ptr6);
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ddrss_phy_writel(DDRSS_DDRPHY_PLLCR0, ctrl->ddrphy_pllcr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DXCCR, cfg->ddrphy_dxccr);
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ddrss_phy_writel(DDRSS_DDRPHY_DSGCR, cfg->ddrphy_dsgcr);
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ddrss_phy_writel(DDRSS_DDRPHY_DCR, cfg->ddrphy_dcr);
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ddrss_phy_writel(DDRSS_DDRPHY_DTPR0, tmg->ddrphy_dtpr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DTPR1, tmg->ddrphy_dtpr1);
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ddrss_phy_writel(DDRSS_DDRPHY_DTPR2, tmg->ddrphy_dtpr2);
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ddrss_phy_writel(DDRSS_DDRPHY_DTPR3, tmg->ddrphy_dtpr3);
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ddrss_phy_writel(DDRSS_DDRPHY_DTPR4, tmg->ddrphy_dtpr4);
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ddrss_phy_writel(DDRSS_DDRPHY_DTPR5, tmg->ddrphy_dtpr5);
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ddrss_phy_writel(DDRSS_DDRPHY_DTPR6, tmg->ddrphy_dtpr6);
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ddrss_phy_writel(DDRSS_DDRPHY_ZQCR, zq->ddrphy_zqcr);
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ddrss_phy_writel(DDRSS_DDRPHY_ZQ0PR0, zq->ddrphy_zq0pr0);
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ddrss_phy_writel(DDRSS_DDRPHY_ZQ1PR0, zq->ddrphy_zq1pr0);
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ddrss_phy_writel(DDRSS_DDRPHY_MR0, ctrl->ddrphy_mr0);
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ddrss_phy_writel(DDRSS_DDRPHY_MR1, ctrl->ddrphy_mr1);
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ddrss_phy_writel(DDRSS_DDRPHY_MR2, ctrl->ddrphy_mr2);
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ddrss_phy_writel(DDRSS_DDRPHY_MR3, ctrl->ddrphy_mr3);
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ddrss_phy_writel(DDRSS_DDRPHY_MR4, ctrl->ddrphy_mr4);
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ddrss_phy_writel(DDRSS_DDRPHY_MR5, ctrl->ddrphy_mr5);
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ddrss_phy_writel(DDRSS_DDRPHY_MR6, ctrl->ddrphy_mr6);
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ddrss_phy_writel(DDRSS_DDRPHY_VTCR0, ctrl->ddrphy_vtcr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0PLLCR0, cfg->ddrphy_dx8sl0pllcr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1PLLCR0, cfg->ddrphy_dx8sl1pllcr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2PLLCR0, cfg->ddrphy_dx8sl2pllcr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DTCR0, ctrl->ddrphy_dtcr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DTCR1, ctrl->ddrphy_dtcr1);
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ddrss_phy_writel(DDRSS_DDRPHY_ACIOCR5, ioctl->ddrphy_aciocr5);
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ddrss_phy_writel(DDRSS_DDRPHY_IOVCR0, ioctl->ddrphy_iovcr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR0, cfg->ddrphy_dx4gcr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR1, cfg->ddrphy_dx4gcr1);
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ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR2, cfg->ddrphy_dx4gcr2);
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ddrss_phy_writel(DDRSS_DDRPHY_DX4GCR3, cfg->ddrphy_dx4gcr3);
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ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR4, cfg->ddrphy_dx0gcr4);
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ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR4, cfg->ddrphy_dx1gcr4);
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ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR4, cfg->ddrphy_dx2gcr4);
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ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR4, cfg->ddrphy_dx3gcr4);
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ddrss_phy_writel(DDRSS_DDRPHY_PGCR5, cfg->ddrphy_pgcr5);
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ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR5, cfg->ddrphy_dx0gcr5);
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ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR5, cfg->ddrphy_dx1gcr5);
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ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR5, cfg->ddrphy_dx2gcr5);
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ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR5, cfg->ddrphy_dx3gcr5);
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ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, DDRSS_DDRPHY_RANKIDR_RANK0);
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ddrss_phy_writel(DDRSS_DDRPHY_DX0GTR0, cfg->ddrphy_dx0gtr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DX1GTR0, cfg->ddrphy_dx1gtr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DX2GTR0, cfg->ddrphy_dx2gtr0);
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ddrss_phy_writel(DDRSS_DDRPHY_DX3GTR0, cfg->ddrphy_dx3gtr0);
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ddrss_phy_writel(DDRSS_DDRPHY_ODTCR, cfg->ddrphy_odtcr);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0IOCR, cfg->ddrphy_dx8sl0iocr);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1IOCR, cfg->ddrphy_dx8sl1iocr);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2IOCR, cfg->ddrphy_dx8sl2iocr);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL0DXCTL2, cfg->ddrphy_dx8sl0dxctl2);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL1DXCTL2, cfg->ddrphy_dx8sl1dxctl2);
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ddrss_phy_writel(DDRSS_DDRPHY_DX8SL2DXCTL2, cfg->ddrphy_dx8sl2dxctl2);
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debug("%s: DDR phy register configuration completed\n", __func__);
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}
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||
|
static int __phy_builtin_init_routine(struct am654_ddrss_desc *ddrss,
|
||
|
u32 init_value, u32 sts_mask,
|
||
|
u32 err_mask)
|
||
|
{
|
||
|
int ret;
|
||
|
|
||
|
ddrss_phy_writel(DDRSS_DDRPHY_PIR, init_value | PIR_INIT_MASK);
|
||
|
|
||
|
sdelay(5); /* Delay at least 10 clock cycles */
|
||
|
|
||
|
if (!wait_on_value(sts_mask, sts_mask,
|
||
|
ddrss->ddrss_phy_cfg + DDRSS_DDRPHY_PGSR0, LDELAY))
|
||
|
return -ETIMEDOUT;
|
||
|
|
||
|
sdelay(16); /* Delay at least 32 clock cycles */
|
||
|
|
||
|
ret = ddrss_phy_readl(DDRSS_DDRPHY_PGSR0);
|
||
|
debug("%s: PGSR0 val = 0x%x\n", __func__, ret);
|
||
|
if (ret & err_mask)
|
||
|
return -EINVAL;
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int write_leveling(struct am654_ddrss_desc *ddrss)
|
||
|
{
|
||
|
int ret;
|
||
|
|
||
|
debug("%s: Write leveling started\n", __func__);
|
||
|
|
||
|
ret = __phy_builtin_init_routine(ddrss, PIR_WL_MASK, PGSR0_WLDONE_MASK,
|
||
|
PGSR0_WLERR_MASK);
|
||
|
if (ret) {
|
||
|
if (ret == -ETIMEDOUT)
|
||
|
printf("%s: ERROR: Write leveling timedout\n",
|
||
|
__func__);
|
||
|
else
|
||
|
printf("%s:ERROR: Write leveling failed\n", __func__);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
debug("%s: Write leveling completed\n", __func__);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int read_dqs_training(struct am654_ddrss_desc *ddrss)
|
||
|
{
|
||
|
int ret;
|
||
|
|
||
|
debug("%s: Read DQS training started\n", __func__);
|
||
|
|
||
|
ret = __phy_builtin_init_routine(ddrss, PIR_QSGATE_MASK,
|
||
|
PGSR0_QSGDONE_MASK, PGSR0_QSGERR_MASK);
|
||
|
if (ret) {
|
||
|
if (ret == -ETIMEDOUT)
|
||
|
printf("%s: ERROR: Read DQS timedout\n", __func__);
|
||
|
else
|
||
|
printf("%s:ERROR: Read DQS Gate training failed\n",
|
||
|
__func__);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
debug("%s: Read DQS training completed\n", __func__);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
int rest_training(struct am654_ddrss_desc *ddrss)
|
||
|
{
|
||
|
int ret;
|
||
|
u32 val;
|
||
|
u32 dgsl0, dgsl1, dgsl2, dgsl3, rddly, rd2wr_wr2rd;
|
||
|
|
||
|
debug("%s: Rest of the training started\n", __func__);
|
||
|
|
||
|
debug("%s: Write Leveling adjustment\n", __func__);
|
||
|
ret = __phy_builtin_init_routine(ddrss, PIR_WLADJ_MASK,
|
||
|
PGSR0_WLADONE_MASK, PGSR0_WLAERR_MASK);
|
||
|
if (ret) {
|
||
|
if (ret == -ETIMEDOUT)
|
||
|
printf("%s:ERROR: Write Leveling adjustment timedout\n",
|
||
|
__func__);
|
||
|
else
|
||
|
printf("%s: ERROR: Write Leveling adjustment failed\n",
|
||
|
__func__);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
debug("%s: Read Deskew adjustment\n", __func__);
|
||
|
ret = __phy_builtin_init_routine(ddrss, PIR_RDDSKW_MASK,
|
||
|
PGSR0_RDDONE_MASK, PGSR0_RDERR_MASK);
|
||
|
if (ret) {
|
||
|
if (ret == -ETIMEDOUT)
|
||
|
printf("%s: ERROR: Read Deskew timedout\n", __func__);
|
||
|
else
|
||
|
printf("%s: ERROR: Read Deskew failed\n", __func__);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
debug("%s: Write Deskew adjustment\n", __func__);
|
||
|
ret = __phy_builtin_init_routine(ddrss, PIR_WRDSKW_MASK,
|
||
|
PGSR0_WDDONE_MASK, PGSR0_WDERR_MASK);
|
||
|
if (ret) {
|
||
|
if (ret == -ETIMEDOUT)
|
||
|
printf("%s: ERROR: Write Deskew timedout\n", __func__);
|
||
|
else
|
||
|
printf("%s: ERROR: Write Deskew failed\n", __func__);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
debug("%s: Read Eye training\n", __func__);
|
||
|
ret = __phy_builtin_init_routine(ddrss, PIR_RDEYE_MASK,
|
||
|
PGSR0_REDONE_MASK, PGSR0_REERR_MASK);
|
||
|
if (ret) {
|
||
|
if (ret == -ETIMEDOUT)
|
||
|
printf("%s: ERROR: Read Eye training timedout\n",
|
||
|
__func__);
|
||
|
else
|
||
|
printf("%s: ERROR: Read Eye training failed\n",
|
||
|
__func__);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
debug("%s: Write Eye training\n", __func__);
|
||
|
ret = __phy_builtin_init_routine(ddrss, PIR_WREYE_MASK,
|
||
|
PGSR0_WEDONE_MASK, PGSR0_WEERR_MASK);
|
||
|
if (ret) {
|
||
|
if (ret == -ETIMEDOUT)
|
||
|
printf("%s: ERROR: Write Eye training timedout\n",
|
||
|
__func__);
|
||
|
else
|
||
|
printf("%s: ERROR: Write Eye training failed\n",
|
||
|
__func__);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
debug("%s: VREF training\n", __func__);
|
||
|
ret = __phy_builtin_init_routine(ddrss, PIR_VREF_MASK, PGSR0_VDONE_MASK,
|
||
|
PGSR0_VERR_MASK);
|
||
|
if (ret) {
|
||
|
if (ret == -ETIMEDOUT)
|
||
|
printf("%s: ERROR: VREF training timedout\n", __func__);
|
||
|
else
|
||
|
printf("%s: ERROR: VREF training failed\n", __func__);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
|
||
|
dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F) >> 2;
|
||
|
dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F) >> 2;
|
||
|
dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F) >> 2;
|
||
|
dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F) >> 2;
|
||
|
|
||
|
rddly = dgsl0;
|
||
|
if (dgsl1 < rddly)
|
||
|
rddly = dgsl1;
|
||
|
if (dgsl2 < rddly)
|
||
|
rddly = dgsl2;
|
||
|
if (dgsl3 < rddly)
|
||
|
rddly = dgsl3;
|
||
|
|
||
|
rddly += 5;
|
||
|
|
||
|
/* Update rddly based on dgsl values */
|
||
|
val = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GCR0) & ~0xF00000);
|
||
|
val |= (rddly << 20);
|
||
|
ddrss_phy_writel(DDRSS_DDRPHY_DX0GCR0, val);
|
||
|
|
||
|
val = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GCR0) & ~0xF00000);
|
||
|
val |= (rddly << 20);
|
||
|
ddrss_phy_writel(DDRSS_DDRPHY_DX1GCR0, val);
|
||
|
|
||
|
val = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GCR0) & ~0xF00000);
|
||
|
val |= (rddly << 20);
|
||
|
ddrss_phy_writel(DDRSS_DDRPHY_DX2GCR0, val);
|
||
|
|
||
|
val = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GCR0) & ~0xF00000);
|
||
|
val |= (rddly << 20);
|
||
|
ddrss_phy_writel(DDRSS_DDRPHY_DX3GCR0, val);
|
||
|
|
||
|
/*
|
||
|
* Add system latency derived from training back into rd2wr and wr2rd
|
||
|
* rd2wr = RL + BL/2 + 1 + WR_PREAMBLE - WL + max(DXnGTR0.DGSL) / 2
|
||
|
* wr2rd = CWL + PL + BL/2 + tWTR_L + max(DXnGTR0.DGSL) / 2
|
||
|
*/
|
||
|
|
||
|
/* Select rank 0 */
|
||
|
ddrss_phy_writel(DDRSS_DDRPHY_RANKIDR, 0x00000000);
|
||
|
|
||
|
dgsl0 = (ddrss_phy_readl(DDRSS_DDRPHY_DX0GTR0) & 0x1F);
|
||
|
dgsl1 = (ddrss_phy_readl(DDRSS_DDRPHY_DX1GTR0) & 0x1F);
|
||
|
dgsl2 = (ddrss_phy_readl(DDRSS_DDRPHY_DX2GTR0) & 0x1F);
|
||
|
dgsl3 = (ddrss_phy_readl(DDRSS_DDRPHY_DX3GTR0) & 0x1F);
|
||
|
|
||
|
/* Find maximum value across all bytes */
|
||
|
rd2wr_wr2rd = dgsl0;
|
||
|
if (dgsl1 > rd2wr_wr2rd)
|
||
|
rd2wr_wr2rd = dgsl1;
|
||
|
if (dgsl2 > rd2wr_wr2rd)
|
||
|
rd2wr_wr2rd = dgsl2;
|
||
|
if (dgsl3 > rd2wr_wr2rd)
|
||
|
rd2wr_wr2rd = dgsl3;
|
||
|
|
||
|
rd2wr_wr2rd >>= 1;
|
||
|
|
||
|
/* Now add in adjustment to DRAMTMG2 bit fields for rd2wr and wr2rd */
|
||
|
/* Clear VSWCTL.sw_done */
|
||
|
ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
|
||
|
ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) & ~0x1);
|
||
|
/* Adjust rd2wr */
|
||
|
ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
|
||
|
ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
|
||
|
(rd2wr_wr2rd << 8));
|
||
|
/* Adjust wr2rd */
|
||
|
ddrss_ctl_writel(DDRSS_DDRCTL_DRAMTMG2,
|
||
|
ddrss_ctl_readl(DDRSS_DDRCTL_DRAMTMG2) +
|
||
|
rd2wr_wr2rd);
|
||
|
/* Set VSWCTL.sw_done */
|
||
|
ddrss_ctl_writel(DDRSS_DDRCTL_SWCTL,
|
||
|
ddrss_ctl_readl(DDRSS_DDRCTL_SWCTL) | 0x1);
|
||
|
/* Wait until settings are applied */
|
||
|
while (!(ddrss_ctl_readl(DDRSS_DDRCTL_SWSTAT) & 0x1)) {
|
||
|
/* Do nothing */
|
||
|
};
|
||
|
|
||
|
debug("%s: Rest of the training completed\n", __func__);
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* am654_ddrss_init() - Initialization sequence for enabling the SDRAM
|
||
|
* device attached to ddrss.
|
||
|
* @dev: corresponding ddrss device
|
||
|
*
|
||
|
* Does all the initialization sequence that is required to get attached
|
||
|
* ddr in a working state. After this point, ddr should be accessible.
|
||
|
* Return: 0 if all went ok, else corresponding error message.
|
||
|
*/
|
||
|
static int am654_ddrss_init(struct am654_ddrss_desc *ddrss)
|
||
|
{
|
||
|
int ret;
|
||
|
|
||
|
debug("%s(ddrss=%p)\n", __func__, ddrss);
|
||
|
|
||
|
ddrss_writel(ddrss->ddrss_ss_cfg, DDRSS_V2H_CTL_REG, 0x000073FF);
|
||
|
|
||
|
am654_ddrss_ctrl_configuration(ddrss);
|
||
|
|
||
|
/* Release the reset to the controller */
|
||
|
clrbits_le32(ddrss->ddrss_ss_cfg + DDRSS_SS_CTL_REG,
|
||
|
SS_CTL_REG_CTL_ARST_MASK);
|
||
|
|
||
|
am654_ddrss_phy_configuration(ddrss);
|
||
|
|
||
|
ret = __phy_builtin_init_routine(ddrss, PIR_PHY_INIT, 0x1, 0);
|
||
|
if (ret) {
|
||
|
dev_err(ddrss->dev, "PHY initialization failed %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = __phy_builtin_init_routine(ddrss, PIR_DRAM_INIT,
|
||
|
PGSR0_DRAM_INIT_MASK, 0);
|
||
|
if (ret) {
|
||
|
dev_err(ddrss->dev, "DRAM initialization failed %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = am654_ddrss_dram_wait_for_init_complt(ddrss);
|
||
|
if (ret) {
|
||
|
printf("%s: ERROR: DRAM Wait for init complete timedout\n",
|
||
|
__func__);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = write_leveling(ddrss);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
ret = read_dqs_training(ddrss);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
ret = rest_training(ddrss);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
/* Enabling refreshes after training is done */
|
||
|
ddrss_ctl_writel(DDRSS_DDRCTL_RFSHCTL3,
|
||
|
ddrss_ctl_readl(DDRSS_DDRCTL_RFSHCTL3) & ~0x1);
|
||
|
|
||
|
/* Disable PUBMODE after training is done */
|
||
|
ddrss_phy_writel(DDRSS_DDRPHY_PGCR1,
|
||
|
ddrss_phy_readl(DDRSS_DDRPHY_PGCR1) & ~0x40);
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* am654_ddrss_power_on() - Enable power and clocks for ddrss
|
||
|
* @dev: corresponding ddrss device
|
||
|
*
|
||
|
* Tries to enable all the corresponding clocks to the ddrss and sets it
|
||
|
* to the right frequency and then power on the ddrss.
|
||
|
* Return: 0 if all went ok, else corresponding error message.
|
||
|
*/
|
||
|
static int am654_ddrss_power_on(struct am654_ddrss_desc *ddrss)
|
||
|
{
|
||
|
int ret;
|
||
|
|
||
|
debug("%s(ddrss=%p)\n", __func__, ddrss);
|
||
|
|
||
|
ret = clk_enable(&ddrss->ddrss_clk);
|
||
|
if (ret) {
|
||
|
dev_err(ddrss->dev, "clk_enable() failed: %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = power_domain_on(&ddrss->ddrcfg_pwrdmn);
|
||
|
if (ret) {
|
||
|
dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = power_domain_on(&ddrss->ddrdata_pwrdmn);
|
||
|
if (ret) {
|
||
|
dev_err(ddrss->dev, "power_domain_on() failed: %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
/* VTT enable */
|
||
|
#if CONFIG_IS_ENABLED(DM_REGULATOR)
|
||
|
device_get_supply_regulator(ddrss->dev, "vtt-supply",
|
||
|
&ddrss->vtt_supply);
|
||
|
ret = regulator_set_value(ddrss->vtt_supply, 3300000);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
debug("VTT regulator enabled\n");
|
||
|
#endif
|
||
|
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* am654_ddrss_ofdata_to_priv() - generate private data from device tree
|
||
|
* @dev: corresponding ddrss device
|
||
|
*
|
||
|
* Return: 0 if all went ok, else corresponding error message.
|
||
|
*/
|
||
|
static int am654_ddrss_ofdata_to_priv(struct udevice *dev)
|
||
|
{
|
||
|
struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
|
||
|
phys_addr_t reg;
|
||
|
int ret;
|
||
|
|
||
|
debug("%s(dev=%p)\n", __func__, dev);
|
||
|
|
||
|
ret = clk_get_by_index(dev, 0, &ddrss->ddrss_clk);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "clk_get failed: %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "power_domain_get() failed: %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = power_domain_get_by_index(dev, &ddrss->ddrdata_pwrdmn, 1);
|
||
|
if (ret) {
|
||
|
dev_err(dev, "power_domain_get() failed: %d\n", ret);
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
reg = devfdt_get_addr_name(dev, "ss");
|
||
|
if (reg == FDT_ADDR_T_NONE) {
|
||
|
dev_err(dev, "No reg property for DDRSS wrapper logic\n");
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
ddrss->ddrss_ss_cfg = (void *)reg;
|
||
|
|
||
|
reg = devfdt_get_addr_name(dev, "ctl");
|
||
|
if (reg == FDT_ADDR_T_NONE) {
|
||
|
dev_err(dev, "No reg property for Controller region\n");
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
ddrss->ddrss_ctl_cfg = (void *)reg;
|
||
|
|
||
|
reg = devfdt_get_addr_name(dev, "phy");
|
||
|
if (reg == FDT_ADDR_T_NONE) {
|
||
|
dev_err(dev, "No reg property for PHY region\n");
|
||
|
return -EINVAL;
|
||
|
}
|
||
|
ddrss->ddrss_phy_cfg = (void *)reg;
|
||
|
|
||
|
ret = dev_read_u32_array(dev, "ti,ctl-reg",
|
||
|
(u32 *)&ddrss->params.ctl_reg,
|
||
|
sizeof(ddrss->params.ctl_reg) / sizeof(u32));
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Cannot read ti,ctl-reg params\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = dev_read_u32_array(dev, "ti,ctl-crc",
|
||
|
(u32 *)&ddrss->params.ctl_crc,
|
||
|
sizeof(ddrss->params.ctl_crc) / sizeof(u32));
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Cannot read ti,ctl-crc params\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = dev_read_u32_array(dev, "ti,ctl-ecc",
|
||
|
(u32 *)&ddrss->params.ctl_ecc,
|
||
|
sizeof(ddrss->params.ctl_ecc) / sizeof(u32));
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Cannot read ti,ctl-ecc params\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = dev_read_u32_array(dev, "ti,ctl-map",
|
||
|
(u32 *)&ddrss->params.ctl_map,
|
||
|
sizeof(ddrss->params.ctl_map) / sizeof(u32));
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Cannot read ti,ctl-map params\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = dev_read_u32_array(dev, "ti,ctl-pwr",
|
||
|
(u32 *)&ddrss->params.ctl_pwr,
|
||
|
sizeof(ddrss->params.ctl_pwr) / sizeof(u32));
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Cannot read ti,ctl-pwr params\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = dev_read_u32_array(dev, "ti,ctl-timing",
|
||
|
(u32 *)&ddrss->params.ctl_timing,
|
||
|
sizeof(ddrss->params.ctl_timing) /
|
||
|
sizeof(u32));
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Cannot read ti,ctl-timing params\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = dev_read_u32_array(dev, "ti,phy-cfg",
|
||
|
(u32 *)&ddrss->params.phy_cfg,
|
||
|
sizeof(ddrss->params.phy_cfg) / sizeof(u32));
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Cannot read ti,phy-cfg params\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = dev_read_u32_array(dev, "ti,phy-ctl",
|
||
|
(u32 *)&ddrss->params.phy_ctrl,
|
||
|
sizeof(ddrss->params.phy_ctrl) / sizeof(u32));
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Cannot read ti,phy-ctl params\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = dev_read_u32_array(dev, "ti,phy-ioctl",
|
||
|
(u32 *)&ddrss->params.phy_ioctl,
|
||
|
sizeof(ddrss->params.phy_ioctl) / sizeof(u32));
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Cannot read ti,phy-ioctl params\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = dev_read_u32_array(dev, "ti,phy-timing",
|
||
|
(u32 *)&ddrss->params.phy_timing,
|
||
|
sizeof(ddrss->params.phy_timing) /
|
||
|
sizeof(u32));
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Cannot read ti,phy-timing params\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
ret = dev_read_u32_array(dev, "ti,phy-zq", (u32 *)&ddrss->params.phy_zq,
|
||
|
sizeof(ddrss->params.phy_zq) / sizeof(u32));
|
||
|
if (ret) {
|
||
|
dev_err(dev, "Cannot read ti,phy-zq params\n");
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
/**
|
||
|
* am654_ddrss_probe() - Basic probe
|
||
|
* @dev: corresponding ddrss device
|
||
|
*
|
||
|
* Return: 0 if all went ok, else corresponding error message
|
||
|
*/
|
||
|
static int am654_ddrss_probe(struct udevice *dev)
|
||
|
{
|
||
|
struct am654_ddrss_desc *ddrss = dev_get_priv(dev);
|
||
|
int ret;
|
||
|
|
||
|
debug("%s(dev=%p)\n", __func__, dev);
|
||
|
|
||
|
ret = am654_ddrss_ofdata_to_priv(dev);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
ddrss->dev = dev;
|
||
|
ret = am654_ddrss_power_on(ddrss);
|
||
|
if (ret)
|
||
|
return ret;
|
||
|
|
||
|
ret = am654_ddrss_init(ddrss);
|
||
|
|
||
|
return ret;
|
||
|
}
|
||
|
|
||
|
static int am654_ddrss_get_info(struct udevice *dev, struct ram_info *info)
|
||
|
{
|
||
|
return 0;
|
||
|
}
|
||
|
|
||
|
static struct ram_ops am654_ddrss_ops = {
|
||
|
.get_info = am654_ddrss_get_info,
|
||
|
};
|
||
|
|
||
|
static const struct udevice_id am654_ddrss_ids[] = {
|
||
|
{ .compatible = "ti,am654-ddrss" },
|
||
|
{ }
|
||
|
};
|
||
|
|
||
|
U_BOOT_DRIVER(am654_ddrss) = {
|
||
|
.name = "am654_ddrss",
|
||
|
.id = UCLASS_RAM,
|
||
|
.of_match = am654_ddrss_ids,
|
||
|
.ops = &am654_ddrss_ops,
|
||
|
.probe = am654_ddrss_probe,
|
||
|
.priv_auto_alloc_size = sizeof(struct am654_ddrss_desc),
|
||
|
};
|