mirror of
https://github.com/brain-hackers/u-boot-brain
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346 lines
8.2 KiB
C
346 lines
8.2 KiB
C
![]() |
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Meson G12A USB3+PCIE Combo PHY driver
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*
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* Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
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* Copyright (C) 2019 BayLibre, SAS
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* Author: Neil Armstrong <narmstron@baylibre.com>
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <regmap.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <reset.h>
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#include <bitfield.h>
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#include <generic-phy.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <linux/bitfield.h>
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#define PHY_R0 0x00
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#define PHY_R0_PCIE_POWER_STATE GENMASK(4, 0)
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#define PHY_R0_PCIE_USB3_SWITCH GENMASK(6, 5)
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#define PHY_R1 0x04
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#define PHY_R1_PHY_TX1_TERM_OFFSET GENMASK(4, 0)
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#define PHY_R1_PHY_TX0_TERM_OFFSET GENMASK(9, 5)
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#define PHY_R1_PHY_RX1_EQ GENMASK(12, 10)
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#define PHY_R1_PHY_RX0_EQ GENMASK(15, 13)
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#define PHY_R1_PHY_LOS_LEVEL GENMASK(20, 16)
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#define PHY_R1_PHY_LOS_BIAS GENMASK(23, 21)
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#define PHY_R1_PHY_REF_CLKDIV2 BIT(24)
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#define PHY_R1_PHY_MPLL_MULTIPLIER GENMASK(31, 25)
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#define PHY_R2 0x08
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#define PHY_R2_PCS_TX_DEEMPH_GEN2_6DB GENMASK(5, 0)
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#define PHY_R2_PCS_TX_DEEMPH_GEN2_3P5DB GENMASK(11, 6)
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#define PHY_R2_PCS_TX_DEEMPH_GEN1 GENMASK(17, 12)
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#define PHY_R2_PHY_TX_VBOOST_LVL GENMASK(20, 18)
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#define PHY_R4 0x10
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#define PHY_R4_PHY_CR_WRITE BIT(0)
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#define PHY_R4_PHY_CR_READ BIT(1)
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#define PHY_R4_PHY_CR_DATA_IN GENMASK(17, 2)
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#define PHY_R4_PHY_CR_CAP_DATA BIT(18)
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#define PHY_R4_PHY_CR_CAP_ADDR BIT(19)
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#define PHY_R5 0x14
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#define PHY_R5_PHY_CR_DATA_OUT GENMASK(15, 0)
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#define PHY_R5_PHY_CR_ACK BIT(16)
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#define PHY_R5_PHY_BS_OUT BIT(17)
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struct phy_g12a_usb3_pcie_priv {
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struct regmap *regmap;
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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#endif
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struct reset_ctl_bulk resets;
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};
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static int phy_g12a_usb3_pcie_cr_bus_addr(struct phy_g12a_usb3_pcie_priv *priv,
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unsigned int addr)
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{
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unsigned int val, reg;
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int ret;
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reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, addr);
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regmap_write(priv->regmap, PHY_R4, reg);
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regmap_write(priv->regmap, PHY_R4, reg);
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regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_ADDR);
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
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(val & PHY_R5_PHY_CR_ACK),
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5, 1000);
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if (ret)
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return ret;
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regmap_write(priv->regmap, PHY_R4, reg);
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
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!(val & PHY_R5_PHY_CR_ACK),
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5, 1000);
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if (ret)
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return ret;
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return 0;
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}
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static int
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phy_g12a_usb3_pcie_cr_bus_read(struct phy_g12a_usb3_pcie_priv *priv,
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unsigned int addr, unsigned int *data)
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{
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unsigned int val;
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int ret;
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ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
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if (ret)
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return ret;
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regmap_write(priv->regmap, PHY_R4, 0);
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regmap_write(priv->regmap, PHY_R4, PHY_R4_PHY_CR_READ);
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
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(val & PHY_R5_PHY_CR_ACK),
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5, 1000);
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if (ret)
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return ret;
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*data = FIELD_GET(PHY_R5_PHY_CR_DATA_OUT, val);
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regmap_write(priv->regmap, PHY_R4, 0);
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
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!(val & PHY_R5_PHY_CR_ACK),
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5, 1000);
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if (ret)
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return ret;
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return 0;
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}
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static int
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phy_g12a_usb3_pcie_cr_bus_write(struct phy_g12a_usb3_pcie_priv *priv,
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unsigned int addr, unsigned int data)
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{
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unsigned int val, reg;
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int ret;
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ret = phy_g12a_usb3_pcie_cr_bus_addr(priv, addr);
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if (ret)
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return ret;
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reg = FIELD_PREP(PHY_R4_PHY_CR_DATA_IN, data);
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regmap_write(priv->regmap, PHY_R4, reg);
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regmap_write(priv->regmap, PHY_R4, reg);
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regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_CAP_DATA);
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
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(val & PHY_R5_PHY_CR_ACK),
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5, 1000);
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if (ret)
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return ret;
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regmap_write(priv->regmap, PHY_R4, reg);
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
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(val & PHY_R5_PHY_CR_ACK) == 0,
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5, 1000);
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if (ret)
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return ret;
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regmap_write(priv->regmap, PHY_R4, reg);
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regmap_write(priv->regmap, PHY_R4, reg | PHY_R4_PHY_CR_WRITE);
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
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(val & PHY_R5_PHY_CR_ACK),
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5, 1000);
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if (ret)
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return ret;
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regmap_write(priv->regmap, PHY_R4, reg);
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ret = regmap_read_poll_timeout(priv->regmap, PHY_R5, val,
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(val & PHY_R5_PHY_CR_ACK) == 0,
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5, 1000);
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if (ret)
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return ret;
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return 0;
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}
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static int
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phy_g12a_usb3_pcie_cr_bus_update_bits(struct phy_g12a_usb3_pcie_priv *priv,
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uint offset, uint mask, uint val)
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{
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uint reg;
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int ret;
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ret = phy_g12a_usb3_pcie_cr_bus_read(priv, offset, ®);
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if (ret)
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return ret;
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reg &= ~mask;
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return phy_g12a_usb3_pcie_cr_bus_write(priv, offset, reg | val);
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}
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static int phy_meson_g12a_usb3_init(struct phy *phy)
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{
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struct udevice *dev = phy->dev;
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struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
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unsigned int data;
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int ret;
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/* TOFIX Handle PCIE mode */
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ret = reset_assert_bulk(&priv->resets);
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udelay(1);
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ret |= reset_deassert_bulk(&priv->resets);
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if (ret)
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return ret;
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/* Switch PHY to USB3 */
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regmap_update_bits(priv->regmap, PHY_R0,
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PHY_R0_PCIE_USB3_SWITCH,
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PHY_R0_PCIE_USB3_SWITCH);
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/*
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* WORKAROUND: There is SSPHY suspend bug due to
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* which USB enumerates
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* in HS mode instead of SS mode. Workaround it by asserting
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* LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus
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* mode
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*/
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ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x102d,
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BIT(7), BIT(7));
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if (ret)
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return ret;
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ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x1010, 0xff0, 20);
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if (ret)
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return ret;
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/*
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* Fix RX Equalization setting as follows
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* LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
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* LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
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* LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
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* LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
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*/
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ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1006, &data);
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if (ret)
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return ret;
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data &= ~BIT(6);
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data |= BIT(7);
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data &= ~(0x7 << 8);
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data |= (0x3 << 8);
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data |= (1 << 11);
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ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1006, data);
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if (ret)
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return ret;
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/*
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* Set EQ and TX launch amplitudes as follows
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* LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
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* LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
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* LANE0.TX_OVRD_DRV_LO.EN set to 1.
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*/
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ret = phy_g12a_usb3_pcie_cr_bus_read(priv, 0x1002, &data);
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if (ret)
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return ret;
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data &= ~0x3f80;
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data |= (0x16 << 7);
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data &= ~0x7f;
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data |= (0x7f | BIT(14));
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ret = phy_g12a_usb3_pcie_cr_bus_write(priv, 0x1002, data);
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if (ret)
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return ret;
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/*
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* MPLL_LOOP_CTL.PROP_CNTRL = 8
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*/
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ret = phy_g12a_usb3_pcie_cr_bus_update_bits(priv, 0x30,
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0xf << 4, 8 << 4);
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if (ret)
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return ret;
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regmap_update_bits(priv->regmap, PHY_R2,
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PHY_R2_PHY_TX_VBOOST_LVL,
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FIELD_PREP(PHY_R2_PHY_TX_VBOOST_LVL, 0x4));
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regmap_update_bits(priv->regmap, PHY_R1,
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PHY_R1_PHY_LOS_BIAS | PHY_R1_PHY_LOS_LEVEL,
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FIELD_PREP(PHY_R1_PHY_LOS_BIAS, 4) |
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FIELD_PREP(PHY_R1_PHY_LOS_LEVEL, 9));
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return ret;
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}
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static int phy_meson_g12a_usb3_exit(struct phy *phy)
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{
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struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(phy->dev);
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return reset_assert_bulk(&priv->resets);
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}
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struct phy_ops meson_g12a_usb3_pcie_phy_ops = {
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.init = phy_meson_g12a_usb3_init,
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.exit = phy_meson_g12a_usb3_exit,
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};
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int meson_g12a_usb3_pcie_phy_probe(struct udevice *dev)
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{
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struct phy_g12a_usb3_pcie_priv *priv = dev_get_priv(dev);
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int ret;
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ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
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if (ret)
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return ret;
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ret = reset_get_bulk(dev, &priv->resets);
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if (ret == -ENOTSUPP)
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return 0;
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else if (ret)
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return ret;
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#if CONFIG_IS_ENABLED(CLK)
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ret = clk_get_by_index(dev, 0, &priv->clk);
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if (ret < 0)
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return ret;
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ret = clk_enable(&priv->clk);
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if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
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pr_err("failed to enable PHY clock\n");
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clk_free(&priv->clk);
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return ret;
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}
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#endif
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return 0;
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}
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static const struct udevice_id meson_g12a_usb3_pcie_phy_ids[] = {
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{ .compatible = "amlogic,g12a-usb3-pcie-phy" },
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{ }
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};
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U_BOOT_DRIVER(meson_g12a_usb3_pcie_phy) = {
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.name = "meson_g12a_usb3_pcie_phy",
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.id = UCLASS_PHY,
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.of_match = meson_g12a_usb3_pcie_phy_ids,
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.probe = meson_g12a_usb3_pcie_phy_probe,
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.ops = &meson_g12a_usb3_pcie_phy_ops,
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.priv_auto_alloc_size = sizeof(struct phy_g12a_usb3_pcie_priv),
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};
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