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https://github.com/brain-hackers/u-boot-brain
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162 lines
4.0 KiB
C
162 lines
4.0 KiB
C
![]() |
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Stefan Roese <sr@denx.de>
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*
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* Derived from linux/drivers/phy/ralink/phy-ralink-usb.c
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* Copyright (C) 2017 John Crispin <john@phrozen.org>
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*/
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#include <common.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <regmap.h>
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#include <reset-uclass.h>
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#include <syscon.h>
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#include <asm/io.h>
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#define RT_SYSC_REG_SYSCFG1 0x014
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#define RT_SYSC_REG_CLKCFG1 0x030
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#define RT_SYSC_REG_USB_PHY_CFG 0x05c
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#define OFS_U2_PHY_AC0 0x800
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#define OFS_U2_PHY_AC1 0x804
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#define OFS_U2_PHY_AC2 0x808
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#define OFS_U2_PHY_ACR0 0x810
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#define OFS_U2_PHY_ACR1 0x814
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#define OFS_U2_PHY_ACR2 0x818
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#define OFS_U2_PHY_ACR3 0x81C
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#define OFS_U2_PHY_ACR4 0x820
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#define OFS_U2_PHY_AMON0 0x824
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#define OFS_U2_PHY_DCR0 0x860
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#define OFS_U2_PHY_DCR1 0x864
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#define OFS_U2_PHY_DTM0 0x868
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#define OFS_U2_PHY_DTM1 0x86C
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#define RT_RSTCTRL_UDEV BIT(25)
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#define RT_RSTCTRL_UHST BIT(22)
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#define RT_SYSCFG1_USB0_HOST_MODE BIT(10)
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#define MT7620_CLKCFG1_UPHY0_CLK_EN BIT(25)
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#define MT7620_CLKCFG1_UPHY1_CLK_EN BIT(22)
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#define RT_CLKCFG1_UPHY1_CLK_EN BIT(20)
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#define RT_CLKCFG1_UPHY0_CLK_EN BIT(18)
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#define USB_PHY_UTMI_8B60M BIT(1)
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#define UDEV_WAKEUP BIT(0)
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struct mt76x8_usb_phy {
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u32 clk;
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void __iomem *base;
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struct regmap *sysctl;
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};
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static void u2_phy_w32(struct mt76x8_usb_phy *phy, u32 val, u32 reg)
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{
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writel(val, phy->base + reg);
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}
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static u32 u2_phy_r32(struct mt76x8_usb_phy *phy, u32 reg)
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{
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return readl(phy->base + reg);
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}
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static void mt76x8_usb_phy_init(struct mt76x8_usb_phy *phy)
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{
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u2_phy_r32(phy, OFS_U2_PHY_AC2);
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u2_phy_r32(phy, OFS_U2_PHY_ACR0);
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u2_phy_r32(phy, OFS_U2_PHY_DCR0);
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u2_phy_w32(phy, 0x00ffff02, OFS_U2_PHY_DCR0);
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u2_phy_r32(phy, OFS_U2_PHY_DCR0);
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u2_phy_w32(phy, 0x00555502, OFS_U2_PHY_DCR0);
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u2_phy_r32(phy, OFS_U2_PHY_DCR0);
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u2_phy_w32(phy, 0x00aaaa02, OFS_U2_PHY_DCR0);
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u2_phy_r32(phy, OFS_U2_PHY_DCR0);
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u2_phy_w32(phy, 0x00000402, OFS_U2_PHY_DCR0);
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u2_phy_r32(phy, OFS_U2_PHY_DCR0);
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u2_phy_w32(phy, 0x0048086a, OFS_U2_PHY_AC0);
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u2_phy_w32(phy, 0x4400001c, OFS_U2_PHY_AC1);
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u2_phy_w32(phy, 0xc0200000, OFS_U2_PHY_ACR3);
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u2_phy_w32(phy, 0x02000000, OFS_U2_PHY_DTM0);
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}
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static int mt76x8_usb_phy_power_on(struct phy *_phy)
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{
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struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev);
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u32 t;
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/* enable the phy */
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regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
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phy->clk, phy->clk);
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/* setup host mode */
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regmap_update_bits(phy->sysctl, RT_SYSC_REG_SYSCFG1,
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RT_SYSCFG1_USB0_HOST_MODE,
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RT_SYSCFG1_USB0_HOST_MODE);
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/*
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* The SDK kernel had a delay of 100ms. however on device
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* testing showed that 10ms is enough
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*/
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mdelay(10);
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if (phy->base)
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mt76x8_usb_phy_init(phy);
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/* print some status info */
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regmap_read(phy->sysctl, RT_SYSC_REG_USB_PHY_CFG, &t);
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printf("remote usb device wakeup %s\n",
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(t & UDEV_WAKEUP) ? "enabled" : "disabled");
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if (t & USB_PHY_UTMI_8B60M)
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printf("UTMI 8bit 60MHz\n");
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else
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printf("UTMI 16bit 30MHz\n");
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return 0;
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}
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static int mt76x8_usb_phy_power_off(struct phy *_phy)
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{
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struct mt76x8_usb_phy *phy = dev_get_priv(_phy->dev);
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/* disable the phy */
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regmap_update_bits(phy->sysctl, RT_SYSC_REG_CLKCFG1,
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phy->clk, 0);
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return 0;
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}
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static int mt76x8_usb_phy_probe(struct udevice *dev)
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{
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struct mt76x8_usb_phy *phy = dev_get_priv(dev);
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phy->sysctl = syscon_regmap_lookup_by_phandle(dev, "ralink,sysctl");
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if (IS_ERR(phy->sysctl))
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return PTR_ERR(phy->sysctl);
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phy->base = dev_read_addr_ptr(dev);
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if (!phy->base)
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return -EINVAL;
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return 0;
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}
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static struct phy_ops mt76x8_usb_phy_ops = {
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.power_on = mt76x8_usb_phy_power_on,
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.power_off = mt76x8_usb_phy_power_off,
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};
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static const struct udevice_id mt76x8_usb_phy_ids[] = {
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{ .compatible = "mediatek,mt7628-usbphy" },
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{ }
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};
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U_BOOT_DRIVER(mt76x8_usb_phy) = {
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.name = "mt76x8_usb_phy",
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.id = UCLASS_PHY,
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.of_match = mt76x8_usb_phy_ids,
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.ops = &mt76x8_usb_phy_ops,
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.probe = mt76x8_usb_phy_probe,
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.priv_auto_alloc_size = sizeof(struct mt76x8_usb_phy),
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};
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