2018-05-07 06:58:06 +09:00
|
|
|
/* SPDX-License-Identifier: GPL-2.0+ */
|
2012-12-11 22:34:12 +09:00
|
|
|
/*
|
2015-03-05 08:36:00 +09:00
|
|
|
* (C) Copyright 2010-2015
|
2012-12-11 22:34:12 +09:00
|
|
|
* NVIDIA Corporation <www.nvidia.com>
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef _TEGRA_GP_PADCTRL_H_
|
|
|
|
#define _TEGRA_GP_PADCTRL_H_
|
|
|
|
|
|
|
|
#define GP_HIDREV 0x804
|
|
|
|
|
|
|
|
/* bit fields definitions for APB_MISC_GP_HIDREV register */
|
|
|
|
#define HIDREV_CHIPID_SHIFT 8
|
|
|
|
#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
|
|
|
|
#define HIDREV_MAJORPREV_SHIFT 4
|
|
|
|
#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
|
|
|
|
|
|
|
|
/* CHIPID field returned from APB_MISC_GP_HIDREV register */
|
|
|
|
#define CHIPID_TEGRA20 0x20
|
|
|
|
#define CHIPID_TEGRA30 0x30
|
2013-01-28 22:32:07 +09:00
|
|
|
#define CHIPID_TEGRA114 0x35
|
2014-01-25 04:46:13 +09:00
|
|
|
#define CHIPID_TEGRA124 0x40
|
2015-03-05 08:36:00 +09:00
|
|
|
#define CHIPID_TEGRA210 0x21
|
2012-12-11 22:34:12 +09:00
|
|
|
|
|
|
|
#endif /* _TEGRA_GP_PADCTRL_H_ */
|